3D Stacked Storage Architecture for Faster Memory Control
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Solution Overview
Problem
Conventional storage devices with non-volatile memory, buffer memory, and memory controller on the same plane occupy a large area, reducing integration efficiency, increasing size, and slowing operating speed due to the need for interpreting command signals.
Innovation Solution
The non-volatile memory, buffer memory, and memory controller are integrated into a single stacked chip structure, minimizing connection lengths and eliminating the need for command signal interpretation by direct control signal application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but area occupied increases and operating speed decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple semiconductor substrates (non-volatile memory, buffer memory, and memory controller) are vertically stacked and bonded together, utilizing the vertical dimension to reduce the horizontal footprint while maintaining all necessary functional components within a compact volume.
2Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but operating speed decreases due to command signal interpretation
Solution Approach 1:
By stacking the memory controller directly above the non-volatile memory on separate semiconductor substrates, the patent minimizes the physical distance for signal transmission. This vertical integration eliminates the need for complex command signal interpretation protocols required in planar configurations, thereby improving operating speed while maintaining manageable device complexity.
3Area of stationary object
If components are integrated into a single stacked chip, then area occupied is reduced and operating speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the storage device into distinct functional segments, each implemented as a separate semiconductor substrate. The non-volatile memory, buffer memory, and memory controller are manufactured as individual chips that are subsequently bonded together in a stacked configuration. This segmentation allows for specialized manufacturing processes for each component while achieving high-density integration.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor substrates are vertically stacked and bonded together, with each substrate containing specific functional components. The memory controller substrate is positioned above the non-volatile memory substrate, creating a compact nested arrangement that maximizes space utilization while maintaining clear functional separation.
4Speed
If components are integrated into a single stacked chip, then operating speed is improved by minimizing connection lengths, but device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking to minimize horizontal connection lengths between components. By positioning the memory controller, buffer memory, and non-volatile memory in a vertical stack with direct bonding between substrates, signal transmission paths are dramatically shortened compared to planar layouts, thereby improving operating speed despite increased integration complexity.
Data Source
AI summary
A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.