3D Stacked Storage Memory Architecture for Faster Signal Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional storage devices with non-volatile memory, buffer memory, and memory controllers on the same plane occupy a large area, reducing integration efficiency and increasing size and production costs, while also slowing down operating speed due to the need for command signal interpretation during write and read operations.
Innovation Solution
The storage device is designed with a stacked structure where the non-volatile memory, buffer memory, and memory controller are formed as a single chip, minimizing connection length and eliminating the need for command signal interpretation by directly applying control signals, using a wafer bonding method to connect components and reduce chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but area occupied increases and operating speed decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by bonding multiple semiconductor substrates vertically. The non-volatile memory is formed on a first semiconductor substrate, the buffer memory on a second semiconductor substrate bonded to the first, and the memory controller on a third semiconductor substrate bonded to the second, with connection structures penetrating through the substrates to establish electrical connections.
2Device complexity
If non-volatile memory, buffer memory, and memory controller are disposed on the same plane, then device complexity is reduced, but operating speed decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by bonding multiple semiconductor substrates vertically. The non-volatile memory is formed on a first semiconductor substrate, the buffer memory on a second semiconductor substrate bonded to the first, and the memory controller on a third semiconductor substrate bonded to the second, with connection structures penetrating through the substrates to establish electrical connections.
3Area of stationary object
If wafer bonding method is used to stack semiconductor substrates, then chip size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the storage device into separate functional modules formed on different semiconductor substrates: non-volatile memory on a first substrate, buffer memory on a second substrate, and memory controller on a third substrate. This segmentation allows each module to be manufactured and optimized independently before being bonded together, reducing the overall manufacturing precision requirements compared to forming all components on a single substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the storage device size, improves operating speed, and decreases power consumption by minimizing chip size and eliminating delays associated with chip interfaces.
Implementation Method 1
a first metal pad disposed above the first cell area and a second metal pad disposed above the peripheral circuit are bonded to each other in a direction perpendicular to an upper surface of the first semiconductor substrate
Implementation Method 2
a connection structure penetrating through the second semiconductor substrate and connecting the memory controller to the second semiconductor structure
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A storage device includes a first semiconductor structure (110) having a first cell area (140), with memory cells disposed on a first semiconductor substrate, and a first metal pad (113) disposed above the first cell area (140). A second semiconductor structure (120) has a peripheral circuit area (150) on a second semiconductor substrate (121) and on which peripheral circuits are disposed, a second cell area (160) including a plurality of second memory cells, and a second metal pad (123) bonded to the first metal pad (113). A third semiconductor structure (130) includes a memory controller (170) disposed on a third semiconductor substrate (131) and connected to a third metal pad (180) through a connection via penetrating through the third semiconductor substrate (131). A connection structure (125) penetrates through the second semiconductor substrate (121) and connects the memory controller (170) to the second semiconductor structure (120). The memory controller (170) controls the first and second cell areas (140, 160) based on a signal applied from a host through the third metal pad (180).