Vertically Stacked Sub-Packages With Interposer Bridges
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Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the size of semiconductor packages while maintaining efficient signal and power distribution, particularly in vertically stacked configurations, which affects the operational speed and reliability of semiconductor chips.
Innovation Solution
The proposed stack package design includes vertically stacked sub-packages with interposer bridges and redistributed layer patterns that provide lateral signal and power connections, allowing for efficient electrical connections between semiconductor chips, reducing routing lengths and improving operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor chips are two-dimensionally disposed on the same plane to provide a single semiconductor package, then the planar area and size of the semiconductor package increase, but the signal and power distribution efficiency is maintained
Solution Approach 1:
The patent transitions from two-dimensional planar stacking to three-dimensional vertical stacking by introducing multiple stacked sub-packages connected through interposer bridges. This dimensional change allows signal and power redistribution layers to be formed at different vertical levels, improving distribution efficiency while reducing the planar footprint of the semiconductor package.
2Area of stationary object
If semiconductor chips are vertically stacked in a limited planar area to reduce package size, then the planar area is reduced, but signal and power distribution efficiency deteriorates
Solution Approach 1:
The patent introduces interposer bridges as intermediary structures between stacked sub-packages. These interposer bridges contain through vias that facilitate signal and power connections between different vertical levels, acting as mediators that enable efficient three-dimensional signal and power distribution while maintaining the compact vertical stacking architecture.
3Length of stationary object
If interposer bridges are disposed laterally spaced apart from semiconductor chips to provide connections, then the routing length is reduced, but the device complexity increases
Solution Approach 1:
The patent divides the connection architecture into segmented components: multiple discrete interposer bridges are laterally spaced apart and positioned at specific locations relative to the semiconductor chip. Each interposer bridge handles specific signal and power routing functions, allowing for modular construction and reduced overall routing length while managing complexity through systematic segmentation.
Data Source
AI summary
A stack package includes sub-packages vertically stacked. Each of the sub-packages includes a semiconductor chip having a power pad and a signal pad, a first interposer bridge having a signal through via and a second power through via, and a second interposer bridge having a first power through via. Each of the sub-packages further includes a signal redistributed layer pattern extending to electrically connect the signal pad to a signal connection part and a power redistributed layer pattern to electrically connect the power pad to the first and second power through vias. An upper sub-package of the sub-packages is rotated relative to a lower sub-package, and the rotated upper sub-package is stacked on a lower sub-package of the sub-packages.