Stacked Sub-Packages With Interposing Bridges
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high integration density and compact form factors necessary for high-performance mobile systems, particularly in integrating multiple semiconductor chips while maintaining efficient electrical connections and reducing package thickness.
Innovation Solution
The semiconductor package design incorporates a stack of sub-packages with interposing bridges and through vias, where each sub-package includes a semiconductor chip and an interposing bridge with overlapping through vias for electrical connectivity, allowing for vertical stacking and reduced thickness through redistribution lines and encapsulants, enabling efficient communication between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated into a single package using conventional methods, then package integration density is improved, but package thickness increases
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking configuration, utilizing the third dimension (height/thickness direction) to integrate multiple chips. Multiple sub-packages are stacked vertically with interposing bridges connecting chips across different layers, enabling high integration density while maintaining reduced package thickness through optimized vertical space utilization.
Solution Approach 2:
The patent implements a nested structure where multiple sub-packages containing semiconductor chips are stacked within a single package body. Each sub-package is nested vertically, with interposing bridges providing electrical connections between chips in different nested layers, achieving high integration density without proportionally increasing package thickness.
2Length of stationary object
If multiple semiconductor chips are stacked vertically to reduce package thickness, then electrical connection complexity increases
Solution Approach 1:
The patent introduces interposing bridges as intermediary components between stacked semiconductor chips. These bridges contain through vias that extend through the encapsulant material, providing direct electrical pathways between chips in different sub-packages. This intermediary structure simplifies the electrical connection system by eliminating the need for complex wire bonds or trace routing through multiple encapsulant layers.
Solution Approach 2:
The patent divides the electrical connection system into modular segments: each sub-package contains its own semiconductor chip and associated interposing bridge structure. The through vias in the interposing bridges are segmented into discrete connection points that can be independently configured, allowing flexible electrical routing while maintaining a systematic and manageable connection architecture.
3Reliability
If interposing bridges with through vias are used to connect stacked chips, then manufacturing precision requirements increase
Solution Approach 1:
The patent forms the through vias in the interposing bridges during the encapsulant curing process, before final chip stacking. The encapsulant material is applied with the chip in position, and the through vias are simultaneously formed extending through the encapsulant to predetermined locations. This preliminary formation of connection pathways ensures precise alignment is maintained throughout subsequent stacking operations, reducing the need for high-precision alignment during assembly.
Solution Approach 2:
The encapsulant material serves multiple functions simultaneously: it provides mechanical support for the chip, forms the body of the interposing bridge, and creates the through vias for electrical connections. The encapsulant self-organizes to provide both structural and electrical functions, reducing the need for separate precision-critical manufacturing steps and minimizing cumulative alignment errors.
Data Source
AI summary
A semiconductor package includes a first sub-package on an interconnection layer. A second sub-package and a third sub-package are sequentially stacked on the first sub-package. Each of the first to third sub-packages includes a semiconductor chip and an interposing bridge. The interposing bridge includes a first through via and a second through via. The second sub-package further includes a first redistributed line electrically connecting the semiconductor chip of the second sub-package to the first through via. The third sub-package further includes a second redistributed line electrically connecting the semiconductor chip of the third sub-package to the second through via.