Stacked-Substrate AES ICs for EM Wave Attenuation
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Solution Overview
Problem
AES integrated circuits are susceptible to unauthorized decryption due to electromagnetic waves emitted during encryption and decryption processes, which can be detected and analyzed to infer the encryption key, compromising data security.
Innovation Solution
A stacked-substrate AES integrated circuit device is fabricated with AES logic circuits on a first substrate and memory arrays on a second substrate stacked over the first, with vias connecting them, increasing density and attenuating electromagnetic waves, thus enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES logic circuits are implemented on a substrate, then encryption functionality is achieved, but electromagnetic waves are emitted that can be detected and analyzed to infer encryption keys
Solution Approach 1:
The patent transitions from a planar single-substrate layout to a three-dimensional stacked-substrate architecture. The AES logic circuits are placed on a first substrate while memory arrays are placed on a second substrate stacked above it, separated by a dielectric layer. This spatial separation in the vertical dimension reduces electromagnetic coupling and attenuates emitted waves, making key inference more difficult while maintaining encryption functionality.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the AES logic circuits on the first substrate and the memory arrays on the second substrate. This dielectric layer acts as an electromagnetic shield that attenuates the waves generated by the logic circuits, preventing them from reaching external detectors while still allowing necessary electrical connections through vias.
2Quantity of substance
If memory arrays and AES logic circuits are integrated on the same substrate, then device density is increased, but electromagnetic wave detectability increases
Solution Approach 1:
The patent segments the integrated circuit into two separate substrates: the first substrate contains AES logic circuits while the second substrate contains memory arrays. This segmentation physically separates the electromagnetic wave-generating logic circuits from the memory structures, reducing wave detectability while maintaining high device density through the stacked three-dimensional arrangement.
3Reliability
If a thin second substrate is used in the stacked configuration, then via depth is reduced improving electrical characteristics, but substrate strength is compromised
Solution Approach 1:
The patent employs a composite substrate structure where the second substrate is made thinner (less than 200 nm, or less than 100 nm in some embodiments) to reduce via depth and improve electrical characteristics. The substrate is engineered with appropriate material composition and structural support to maintain sufficient mechanical strength despite the reduced thickness, achieving a balance between electrical performance and structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked-substrate configuration increases memory array density and significantly reduces the detectability of electromagnetic waves emitted by AES logic circuits, making unauthorized decryption more difficult and improving overall encryption security.
Implementation Method 1
the second substrate stacked over the first, with vias connecting them, increasing density and attenuating electromagnetic waves
Data Source
AI summary
A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.