Stacked-Substrate Display Wiring for High-Resolution Head-Mounted Displays
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Solution Overview
Problem
Existing head-mounted display devices face challenges in achieving high-resolution images due to the limitations of current display technologies, particularly in efficiently connecting multiple semiconductor substrates without interference, which affects manufacturing yield and performance.
Innovation Solution
The use of a micro display device with a layout design that includes two different single crystal semiconductor substrates, connected by efficient wiring layouts that avoid interference, utilizing a connection line layer with conductive vias and bridge lines to electrically connect pixel circuits and sub-pixels, allowing for improved manufacturing yield and reduced substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor substrates are connected using conventional wiring layouts, then electrical connection between substrates is achieved, but wiring interference occurs which reduces manufacturing yield
Solution Approach 1:
The patent introduces a multi-layer connection structure with first and second connection lines disposed in different layers. The first connection lines connect first sub-pixels to first pixel circuits, while the second connection lines connect second sub-pixels to second pixel circuits. By separating the wiring into different spatial layers, the patent eliminates wiring interference between adjacent circuits, thereby improving manufacturing yield without compromising electrical connection functionality.
2Area of stationary object
If substrate area is reduced to meet head-mounted display requirements, then device portability is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent divides the display substrate into multiple independent regions, each containing sub-pixels and pixel circuits that are independently connected through dedicated first and second connection lines. This segmentation allows each region to be manufactured and connected independently, reducing the overall manufacturing difficulty while maintaining high precision. The modular approach enables better control over manufacturing processes even in reduced substrate areas.
3Measurement precision
If high-resolution display is implemented, then image quality is improved, but device complexity increases
Solution Approach 1:
The patent employs a multi-layer connection architecture where first connection lines and second connection lines are disposed in different layers to connect sub-pixels to pixel circuits. This three-dimensional wiring approach allows high-resolution displays with multiple sub-pixels per pixel to be implemented without proportionally increasing planar wiring complexity. The vertical separation of connection lines in different layers reduces routing complexity while maintaining the high pixel density required for high-resolution displays.
Data Source
AI summary
A display device and a head mounted display device are provided. A display device includes: a first single crystal semiconductor substrate on which a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction is located, the plurality of pixel circuits including a first transistor; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate on which a plurality of sub-pixels including a plurality of light emitting elements and arranged along the first direction and the second direction is located; and a connection line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and including a plurality of bridge lines, each of the plurality of bridge lines electrically connected to one of the plurality of pixel circuits and one of the plurality of sub-pixels.