Stacked Substrate Interconnect for Light-Accessible FSI-CIS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional stacked integrated chip structures are not suitable for front-side illuminated CMOS image sensors (FSI-CIS) as they do not allow light to pass through, limiting their integration into multi-dimensional integrated chip structures.
Innovation Solution
A method of forming a multi-dimensional integrated chip with tiers connected in a front-to-back configuration, where a first dielectric structure is bonded to the back-side of a second substrate, and an inter-tier interconnect structure with segments of varying sidewall angles is used to electrically couple metal interconnect layers, allowing FSI-CIS to be integrated as front-side image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If conventional stacked integrated chip structures are used, then electrical interconnection between substrates is achieved, but light cannot pass through the structure
Solution Approach 1:
The interconnect structure is divided into multiple segments with different sidewall angles. The first segment has a first sidewall angle and the second segment has a second sidewall angle that is different from the first. This segmentation allows light to pass through certain angular ranges while maintaining electrical connectivity, resolving the contradiction between light transmission and electrical interconnection.
Solution Approach 2:
Different portions of the interconnect structure have different geometric properties. The first segment and second segment have different sidewall angles, creating local variations in the structure that allow simultaneous light transmission and electrical connectivity. This local quality differentiation enables FSI-CIS integration while maintaining the stacked architecture.
2Illumination intensity
If FSI-CIS are integrated into stacked structures, then light can reach image sensing elements, but electrical connectivity between tiers must be maintained
Solution Approach 1:
The interconnect is segmented into multiple portions with different sidewall angles, where the first segment and second segment have distinct angular characteristics. This segmentation enables the structure to simultaneously provide light transmission paths and reliable electrical connectivity, allowing FSI-CIS to function properly while maintaining tier-to-tier electrical connections.
Solution Approach 2:
The interconnect structure employs asymmetric geometry with different sidewall angles in different segments. This asymmetry creates directional properties that allow light to pass through while maintaining electrical connectivity, enabling FSI-CIS integration without compromising the reliability of electrical connections between stacked substrates.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.