Stacked Substrate Imaging Device With Through-Via Relay
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Solution Overview
Problem
Current solid-state imaging devices, such as CCD and CMOS image sensors, face limitations in achieving high-speed reading with small chip area, restricted layout, and deteriorated pixel characteristics, including motion blur and increased parasitic capacitance, which hinder global shutter reading and pixel connectivity.
Innovation Solution
A solid-state imaging device with a stacked substrate configuration, where a photosensitive part on one substrate is connected to charge storage and output parts on another substrate via through-vias, allowing for efficient charge transfer and relay, enabling high-speed reading and reduced chip area while minimizing layout restrictions and pixel flaws.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a stacked substrate configuration is used to reduce chip area, then chip area is reduced, but connection complexity between substrates increases
Solution Approach 1:
The device is divided into multiple substrates (first substrate with photosensitive part, second substrate with charge storage and output parts) that can be manufactured independently and then stacked. This segmentation allows each substrate to be optimized separately while reducing the overall chip area through vertical integration.
Solution Approach 2:
Through-vias are introduced as intermediary connection structures that pass through the substrates to establish electrical connections between the photosensitive part on the first substrate and the charge storage/output parts on the second substrate. These through-vias simplify the connection process between stacked substrates.
2Productivity
If charge transfer parts are connected to charge storage parts via through-vias, then reading speed is improved, but parasitic capacitance increases
Solution Approach 1:
The connection between charge transfer parts and charge storage parts is moved from a planar (2D) arrangement to a vertical (3D) arrangement using through-vias. This dimensional change reduces the horizontal distance for charge transfer, improving reading speed while the vertical path minimizes parasitic capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed reading with a small chip area, suppresses white flaws and pixel characteristic deterioration, and allows for global shutter functionality without additional pixel structure, reducing power consumption and enhancing digital output conversion and on-chip signal processing.
Implementation Method 1
a solid-state imaging device using a photoelectric conversion element which detects light and generates a charge
Data Source
AI summary
This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed. The first substrate and second substrate are stacked together, and the relay part 240 electrically couples the charge transfer parts of the first substrate to the charge storage parts of the second substrate by means of a connecting parts passing through the substrates outside the photosensitive region of the photosensitive part.