Stacked Substrate Inductor for Reduced Package Height
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional device packages with separate SMD power inductors reduce integration density, increase footprint, and elevate costs due to the separate inductor's height when mounted on an interposer substrate.
Innovation Solution
A stacked substrate inductor design where a first substrate with a first inductor is stacked on a second substrate with a second inductor, both substrates potentially including inductance loops and a magnetic core, with an inductor interconnect electrically coupling the first and second inductors, allowing for overlapping core regions to enhance inductance and reduce package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate SMD power inductor is mounted on the interposer substrate, then the inductor can be provided as a standalone device, but the total height of the device package increases
Solution Approach 1:
The patent merges the SMD power inductor with the interposer substrate by forming the inductor directly within the substrate using conductive traces and vias. This integration eliminates the need for a separate mounted inductor component, thereby reducing the total package height while maintaining the inductor's standalone functional capability through its embedded design.
Solution Approach 2:
The patent transitions the inductor from a three-dimensional mounted component to a two-dimensional planar structure embedded within the substrate. By configuring conductive traces in spiral or loop patterns on substrate layers and connecting them through vias, the inductor functionality is achieved in a flattened configuration that reduces vertical height while preserving inductance properties.
2Ease of manufacture
If a separate SMD power inductor is mounted on the interposer substrate, then the inductor can be easily installed, but the integration density is reduced
Solution Approach 1:
The patent combines the inductor structure with the interposer substrate as a single integrated component. The conductive traces and vias are formed as part of the substrate manufacturing process, eliminating the separate installation step while achieving higher integration density by occupying the same physical space that would otherwise be taken by both the substrate and a mounted inductor.
Solution Approach 2:
The patent segments the inductor into multiple conductive trace layers and via connections distributed across different substrate layers. This segmentation allows the inductor to be embedded within the substrate structure itself, enabling the manufacturing process to produce both the substrate and inductor simultaneously through standard PCB fabrication techniques, thereby improving integration density without compromising ease of manufacture.
3Ease of repair
If a separate SMD power inductor is mounted on the interposer substrate, then the inductor can be independently replaced, but the total footprint increases
Solution Approach 1:
The patent integrates the inductor within the substrate, which reduces the device footprint by eliminating the additional space required for a mounted inductor. While this reduces the area, it also limits replaceability, so the design must balance compactness with repairability considerations through modular substrate design or accessible test points.
4Adaptability or versatility
If a separate SMD power inductor is mounted on the interposer substrate, then the inductor can be independently selected, but the costs increase
Solution Approach 1:
The patent integrates the inductor within the substrate using standard conductive materials and manufacturing processes, which reduces the overall cost by eliminating the need for separate inductor components and their associated mounting hardware. The inductor is formed as part of the substrate fabrication process, reducing assembly steps and material costs while maintaining design flexibility through configurable trace geometries.
Solution Approach 2:
The patent enables different inductor values and characteristics by varying the geometric parameters of the conductive traces (such as trace width, spacing, spiral radius, and number of turns) during substrate manufacturing. This allows for cost-effective customization of inductor properties without requiring different physical components, thereby reducing costs while maintaining selection flexibility through design variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked substrate inductor design reduces the overall device package height while maintaining or exceeding the inductance of conventional SMD power inductors, enhancing integration density and flexibility, and reducing costs.
Implementation Method 1
A core region of the first inductor may be referred to as a first core region, and a core region of the second inductor may be referred to as a second core region. At least a portion of the first core region may overlap with at least a portion of the second core region.
Data Source
AI summary
In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.