Stacked Substrate Interconnect Packaging for Smaller, Reliable Electronics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electronic package manufacturing methods result in high costs, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
The proposed solution involves a method for manufacturing electronic devices using a first and second substrate with dielectric and conductive structures, interconnect structures, and encapsulants, where the interconnect structures are provided on a carrier and bonded with temporary adhesive layers, allowing for efficient assembly and size reduction through advanced materials and processes like electrolytic plating and encapsulant application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electronic package manufacturing methods are used, then manufacturing cost is reduced, but reliability decreases and package size becomes too large
Solution Approach 1:
The patent implements nested packaging by placing one electronic package inside another package structure. The inner package containing the first electronic component is positioned within an outer package structure, allowing multiple components to be integrated in a compact arrangement. This nesting approach reduces the overall package volume while maintaining proper isolation and connection between components, thereby improving reliability without increasing package size.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked packaging by positioning electronic components at different vertical levels. The first electronic component is placed in a first plane, while the second electronic component is placed in a second plane at a different height, connected through vertical interconnect structures. This dimensional change allows efficient use of space, reducing package footprint while maintaining component reliability through proper spacing and connection pathways.
2Productivity
If conventional electronic package manufacturing methods are used, then manufacturing simplicity is maintained, but performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-forming interconnect structures on substrates before final package assembly. The conductive interconnect structures are fabricated on the substrate surfaces in advance, with predetermined patterns and connections. This preliminary preparation enables more efficient subsequent assembly operations, improving manufacturing productivity while ensuring reliable electrical connections are already in place before components are mounted and sealed.
Solution Approach 2:
The patent merges multiple manufacturing operations into an integrated process flow. The formation of dielectric layers, conductive interconnect structures, and encapsulation is combined into a unified manufacturing sequence where steps are performed in an integrated manner rather than as separate discrete operations. This merging of operations improves manufacturing efficiency and consistency while maintaining high reliability standards throughout the process.
3Volume of stationary object
If conventional electronic package manufacturing methods are used, then manufacturing cost is reduced, but package size becomes too large
Solution Approach 1:
The patent segments the package structure into distinct functional modules: substrates with patterned interconnect structures, electronic components mounted on specific planes, dielectric layers providing isolation, and encapsulation structures. Each segment is designed and fabricated with specific functions, allowing complex packaging requirements to be broken down into manageable manufacturing steps. This segmentation enables precise control over package dimensions while managing manufacturing complexity through modular construction.
Solution Approach 2:
The patent utilizes parameter changes in the manufacturing process to achieve compact packaging. By controlling parameters such as dielectric layer thickness, interconnect structure dimensions, and component placement positions, the package size is optimized. The dielectric layers are formed with specific thickness parameters to provide adequate isolation while minimizing vertical space. Interconnect structures are dimensioned with precise parameters to achieve low resistance connections without excessive size, thereby reducing overall package volume while managing manufacturing complexity through controlled parameter specifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process efficiency, reduces package size, and improves reliability and performance by allowing for precise control over interconnects and encapsulants, addressing the limitations of traditional methods.
Implementation Method 1
conductive structure formed by electrolytic plating
Data Source
AI summary
In one example, an electronic device comprises a first substrate comprising a first dielectric structure and a first conductive structure, a first interconnect structure over an inward side of the first substrate and coupled with the first conductive structure, a first encapsulant over the inward side of the first substrate and contacting a lateral side of the first interconnect structure, a second substrate over the first encapsulant and comprising a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled with the first interconnect structure, and a first electronic component coupled with an outward side of the first substrate. The first electronic component is coupled with the second conductive structure via the first interconnect structure and the first conductive structure. Other examples and related methods are also disclosed herein.