Stacked Substrate Power Module for Parasitic Inductance Reduction
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Solution Overview
Problem
Existing power modules suffer from high parasitic inductance, which limits switching speed and peak current handling, leading to reliability issues due to over-current and over-voltage stresses.
Innovation Solution
A stacked substrate arrangement with direct bonded copper substrates and a dielectric layer to increase mutual inductance by tightly coupling source and return current paths, reducing parasitic inductance through strategic placement and thickness of the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional power module structures are used, then manufacturing and assembly are simpler, but parasitic inductance is high which limits switching speed and peak current handling
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked substrate configuration. Multiple substrates are vertically stacked with conductive layers arranged in different planes, creating tightly-coupled source and return current paths that reduce parasitic inductance while enabling faster switching speeds and higher peak current handling capability.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers are embedded within stacked substrates. The source and return current paths are nested within adjacent conductive layers, creating intimate magnetic coupling that reduces loop inductance. This nested arrangement allows current paths to be closely intertwined in three-dimensional space, achieving low parasitic inductance without excessive external complexity.
2Reliability
If stacked substrate arrangement with tight coupling is used, then parasitic inductance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the power module into multiple discrete substrates that can be manufactured and assembled separately. Each substrate contains specific conductive layers and power semiconductor switches, allowing for modular manufacturing. This segmentation enables precise alignment at each interface while simplifying the overall manufacturing process, as each substrate can be prepared independently with standard precision requirements.
3Power
If conventional current paths are used, then device structure is simpler, but peak current handling capability is limited due to high parasitic inductance
Solution Approach 1:
The patent utilizes three-dimensional spatial arrangement of conductive layers across stacked substrates to reduce current loop area. By arranging source and return current paths in adjacent layers vertically stacked rather than laterally separated, the current loops are compressed in the vertical dimension, reducing parasitic inductance and enabling higher peak current handling capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic inductance, enhancing switching speed and peak current handling while maintaining thermal conductivity and adaptability for various power semiconductor switch configurations.
Implementation Method 1
The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the first and second electrically-conductive layers. The level of coupling arranged to increase the mutual inductance within the power module.
Data Source
AI summary
Power modules with reduced parasitic inductances are provided. A power module includes a first substrate including a first electrically-conductive layer and a second substrate including a second electrically-conductive layer. These substrates may be stacked on each other. A scalable network of power switches may be arranged on the substrates. Power bars may be connectable to the electrically-conductive layers through electromechanical interfaces at selectable interface locations. The locations and/or type of interface may be selectable based on the arrangement of the switches. The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the electrically-conductive layers. The level of coupling may be arranged to increase the mutual inductance within the power module, which can effectively reduce the formation of parasitic inductance in the power module.