Stacked Semiconductor Substrates for Isolation and Thermal Load

The patent applies preliminary action by forming the insulating isolation region before creating the through-holes and subsequent structures. This early formation allows the isolation region to be established as a foundation layer, enabling better thermal management in later processing steps while maintaining element isolation performance. The isolation region is formed as a preliminary structure that supports subsequent high-temperature processing without compromising element separation.

The patent introduces a mandrel as an intermediary object to define gate width. Instead of using element isolation portions directly for gate width definition, the mandrel serves as a temporary intermediate structure that enables precise gate patterning. The mandrel is formed, patterned, and then removed, leaving behind precisely defined gate structures. This intermediary approach resolves the unsuitability of direct isolation-based gate definition while maintaining manufacturing feasibility.

The patent applies segmentation by dividing the overall device into multiple separate substrates (first substrate with photoelectric conversion elements, second substrate with through-holes). This segmentation allows each substrate to be optimized independently for its specific function while maximizing the area available for signal processing units on the first substrate. The segmented approach improves imaging performance by dedicating full substrate area to light-sensitive elements without circuit interference, while the complexity of joining is managed through standardized through-hole formation and alignment processes.