Stacked Carrier Substrates for Low-Inductance Power Converters
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Solution Overview
Problem
Existing power electronics converters in aerospace applications face limitations in efficiency and power-to-weight ratio due to high parasitic inductance in commutation cells, which leads to switching losses and heat generation, limiting performance improvements beyond semiconductor technology advancements.
Innovation Solution
The design of power electronics converters with surface-mounted power semiconductors, encapsulation in pre-packages, and direct electrical connections via vias in a vertical direction, utilizing multi-layer carrier substrates to reduce parasitic inductance while adhering to spatial constraints, incorporating SiC or GaN MOSFETs and capacitors to enhance efficiency and power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power module topology is used with traditional electrical connections, then converter cost and availability are acceptable, but parasitic inductance is high leading to switching losses and limited efficiency
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional stacked carrier substrates connected via vertical vias. This dimensional change allows direct vertical connections between power semiconductor devices on different substrates, dramatically reducing parasitic inductance and switching losses while maintaining acceptable structural complexity.
Solution Approach 2:
The patent implements nested carrier substrates where multiple substrate layers are stacked and interconnected through vias. Power semiconductor devices are embedded within encapsulation materials on each substrate layer, creating a nested structure that minimizes connection paths and reduces parasitic inductance.
2Productivity
If converter efficiency is improved through semiconductor technology advances, then performance increases, but parasitic inductance from electrical connections remains a limiting factor
Solution Approach 1:
The patent extracts and eliminates the problematic horizontal electrical connection paths that generate parasitic inductance. By using vertical via connections between stacked substrates, the design removes the source of parasitic inductance while maintaining all necessary electrical connections, thereby reducing switching losses and improving overall converter efficiency.
3Loss of energy
If multi-layer carrier substrates with vertical vias are used, then parasitic inductance is reduced and efficiency increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the converter into multiple independent carrier substrate layers, each containing specific power semiconductor devices and connection structures. This segmentation allows parallel manufacturing of individual substrate layers using standard PCB techniques, which can then be assembled through vertical via connections, reducing overall manufacturing complexity compared to creating a single complex multi-layer structure.
4Power
If surface-mounted power semiconductors with direct via connections are implemented, then power density increases, but spatial constraints in aerospace applications must be strictly adhered to
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple carrier substrates and connecting them through vertical vias. This three-dimensional arrangement consolidates electrical connections and reduces the horizontal footprint of the converter, thereby increasing power density while maintaining compact volume suitable for aerospace applications.
Data Source
AI summary
A power electronics converter may include: a first multi-layer planar carrier substrate having one or more electrically conductive layers; a second multi-layer planar carrier substrate having one or more electrically conductive layers; a converter commutation cell circuit including a plurality of commutation cell components that are electrically connected together via the one or more electrically conductive layers of the first planar carrier substrate and electrical connections, the commutation cell components including one or more power semiconductor switching elements in one or more power semiconductor prepackages, each power semiconductor prepackage including a power semiconductor switching element embedded in a solid insulating material; one or more additional converter components electrically connected to the one or more electrically conductive layers of the second planar carrier substrate; and one or more further electrical connections connecting together one or more of the electrically conductive layers of the first carrier substrate and the second carrier substrate.