Interconnected Stacked Substrates Without Encapsulant Separation
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Solution Overview
Problem
Conventional package on package (PoP) technology faces issues with voids in conductive pillars due to thermal stress and separation of encapsulant from substrates with different thermal expansion coefficients, leading to damage and deteriorated electrical transmission.
Innovation Solution
A stacked package device design without encapsulant, featuring interconnected substrates with flip-chips and external connecting members, eliminating the need for copper pillars and preventing separation due to thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulant is used to fill space between substrates and encapsulate chips, then chips are protected and space is filled, but separation occurs between encapsulant and substrates due to different coefficients of thermal expansion when heated
Solution Approach 1:
The patent removes the encapsulant entirely from the package structure. Instead of using encapsulant to fill space and protect chips, the design relies on the substrate cavity structure and direct chip mounting to provide protection, thereby eliminating the thermal expansion mismatch problem that causes separation between encapsulant and substrates.
2Reliability
If conductive pillars are formed by electroplating process, then electrical connection is established between substrates, but voids are formed in conductive pillars which cause damage under thermal stress and deteriorate electrical transmission
Solution Approach 1:
The patent eliminates the electroplated conductive pillars entirely. Instead of forming conductive pillars through electroplating (which creates voids), the design uses direct flip-chip bonding with solder balls or conductive paste to establish electrical connections, thereby avoiding the void formation and subsequent thermal stress damage.
3Volume of moving object
If conventional PoP technology with encapsulant and conductive pillars is used, then packages are integrated and space is reduced, but thermal stress causes separation and damage leading to deteriorated electrical transmission
Solution Approach 1:
The patent removes both the encapsulant and conductive pillars from the conventional PoP structure. The simplified design uses substrates with cavities for chip mounting and direct electrical connections, eliminating the sources of thermal stress damage while maintaining compact packaging through vertical stacking and cavity utilization.
Solution Approach 2:
The patent employs composite substrate structures with cavities that provide both mechanical support and electrical interconnection functions. The substrate design integrates multiple functions (structural support, electrical connection, chip mounting) into a unified composite structure, improving reliability while maintaining compact form factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design avoids separation and damage to conductive pillars, maintaining electrical integrity by using flip-chips and external connecting members, thus enhancing structural stability and electrical performance.
Implementation Method 1
first flip-chip electrically mounted on the inner bottom surface of the chip cavity
Implementation Method 2
electrically connected to the first package
Implementation Method 3
multiple external connecting members are provided on the outer surface of the second substrate
Data Source
AI summary
A stacked package has a first package and a second package vertically stacked and electrically connected to each other. Any one or each of the first package and the second package includes a first substrate and a second substrate, wherein a chip cavity is formed on an inner surface of the first substrate and a first flip-chip is mounted in the chip cavity. A second flip-chip facing the chip cavity is mounted on an inner surface of the second substrate. Multiple inner pads are respectively formed on opposite surfaces of the first and the second substrates for interconnecting the substrates electrically. Because no encapsulant is provided to cover the first flip-chip and the second flip-chip, the problem of separation between the encapsulant and the substrates is avoided.