Stacked Power Switch Cell Layout for Lower On-Resistance
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Solution Overview
Problem
Current integrated circuit devices face challenges in increasing integration density and reducing power leakage in the middle-of-line (MOL) and back-end-of-line (BEOL) portions of device fabrication, particularly in the on-resistance of power switch cells, which affects operation speed and power efficiency.
Innovation Solution
The integration of stacked transistors with upper and lower transistors of the same conductivity type, electrically connected in parallel, reduces on-resistance without increasing area, utilizing a power switch cell structure that includes a common gate electrode for both transistors and conductive contacts to connect source/drain regions, thereby enhancing power efficiency and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If stacked transistors are integrated with upper and lower transistors of the same conductivity type electrically connected in parallel, then on-resistance decreases and power efficiency improves, but device complexity increases
Solution Approach 1:
The patent implements stacked transistors in the vertical dimension with upper and lower transistors stacked above each other, transitioning from a planar two-dimensional layout to a three-dimensional vertical structure. This dimensional change allows parallel connection of transistors of the same conductivity type without increasing lateral area, thereby reducing on-resistance and power leakage while maintaining compact footprint
Solution Approach 2:
The patent merges multiple transistor functions into a single stacked structure where upper and lower transistors are electrically connected in parallel. This combining of transistors into one integrated stack achieves equivalent parallel connection benefits (reduced on-resistance) while consolidating what would otherwise be separate devices into a unified structure
2Speed
If stacked transistors are integrated with upper and lower transistors of the same conductivity type electrically connected in parallel, then operation speed improves, but device complexity increases
Solution Approach 1:
By stacking transistors vertically in the third dimension, the patent achieves parallel electrical connection of upper and lower transistors without increasing lateral footprint. This vertical integration provides multiple current paths that reduce on-resistance and improve operation speed, while the compact 3D structure avoids the area penalty that would normally accompany parallel transistor implementations
Solution Approach 2:
The patent changes the electrical connection configuration by electrically connecting the upper and lower gate electrodes together, transforming the stacked transistor structure into an equivalent parallel connection. This parameter change in the electrical connectivity enables reduced on-resistance and improved operation speed while maintaining a compact vertical structure
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Integrated circuit devices may include a power switch cell including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper channel region, first and second upper source/drain regions, and an upper gate electrode on the upper channel region. The lower transistor may include a lower channel region, first and second lower source/drain regions, and a lower gate electrode on the lower channel region. The first and second upper source/drain regions and the first and second lower source/drain regions may have the same conductivity type, the first upper source/drain region and the first lower source/drain region may be electrically connected to each other, the second upper source/drain region and the second lower source/drain region may be electrically connected to each other, and the upper and lower gate electrodes may be electrically connected to each other.