Stacked Switching Circuits for DRAM Memory Modules
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Solution Overview
Problem
Current memory system architectures face limitations in scalability and latency due to the unbuffered data interface in traditional DIMMs, which restricts the number of DIMMs that can be utilized and introduces undesirable latencies when multiple DIMMs are on the same data channel.
Innovation Solution
A memory subsystem with a host coupled to multiple memory modules, each equipped with stacked switching circuits that route data between memory modules and the memory controller using bi-directional serial links, allowing for efficient data serialization and deserialization, and enabling each switching circuit to access fewer than all memory chips on a module, with the option of stacking circuitry on flexible boards to optimize space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMMs are placed on the same data channel, then memory capacity is increased, but memory access latency increases and data rates are insufficient
Solution Approach 1:
The patent segments the memory system into multiple independent data channels, each capable of handling multiple DIMMs. Instead of placing all DIMMs on a single shared channel, the system divides the memory controller into multiple channel controllers, each managing its own dedicated channel. This segmentation allows parallel access to multiple DIMMs across different channels, reducing latency while maintaining high capacity.
Solution Approach 2:
The patent introduces advanced memory buffers (AMB) as intermediary components between the memory controller and DIMMs. These buffers cache data from multiple DIMMs and manage data flow, allowing the controller to access data from any DIMM without waiting for the physical location. The AMB acts as a mediator that decouples the controller from the physical DIMM arrangement, reducing access latency while supporting high capacity configurations.
2Device complexity
If traditional unbuffered DIMMs are used, then device complexity is reduced, but scalability and data rates are limited
Solution Approach 1:
The patent merges the functionality of traditional DIMMs with advanced memory buffers into an integrated FB-DIMM module. The buffer chip is physically combined with the memory chips on the same DIMM module, creating a unified component that provides both high capacity and high data rates. This merging allows the system to maintain simple module-level architecture while achieving enhanced scalability through the integrated buffer functionality.
3Productivity
If FB-DIMMs with buffer chips are implemented, then data rates and scalability are improved, but device complexity increases
Solution Approach 1:
The patent designs the advanced memory buffer to perform multiple functions: caching data from multiple DIMMs, managing data flow between controller and memory, providing error correction, and enabling address translation. This multi-functional buffer design consolidates what would otherwise require separate components, achieving high data rates and scalability without proportionally increasing complexity.
Data Source
AI summary
A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data. Switching circuits may be coupled to a stacked memory chip via a flexible interconnect, and may also be manufactured side by side with a corresponding memory chip on a flexible circuit board.