Stacked Switching Element Layout for Semiconductor Surge Suppression
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Solution Overview
Problem
Semiconductor devices with high-voltage and low-voltage switching elements experience surge voltage issues due to inductance components in the connection path, particularly when capacitors are connected between input-side terminals, exacerbated by high switching speeds.
Innovation Solution
A semiconductor device design featuring switching elements connected in series with a capacitor in parallel, where the capacitor overlaps with the switching elements to reduce inductance components and suppress surge voltages, utilizing a configuration that minimizes the inductance in the conduction paths and allows for reduced mounting area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is connected between input-side terminals with conventional layout, then the semiconductor device can filter voltage ripple, but the inductance component in the connection path generates surge voltage during switching
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked configuration where the capacitor is positioned vertically above or below the switching elements. This dimensional change allows the capacitor to be electrically connected to the switching elements through short vertical paths, dramatically reducing the loop area and inductance of the connection path while maintaining effective voltage ripple filtering
Solution Approach 2:
The patent integrates the capacitor and switching elements into a single stacked structure where they are physically and electrically combined. The capacitor is directly connected to the switching elements through minimal interconnection paths, merging the filtering function with the switching function in a compact integrated arrangement that eliminates long external connection paths
2Productivity
If switching speed is increased to improve productivity, then the semiconductor device can process signals faster, but the inductance component generates higher surge voltage
Solution Approach 1:
By stacking the capacitor vertically relative to the switching elements, the patent creates short vertical connection paths that minimize inductance. This three-dimensional arrangement allows high-speed switching operations without generating excessive surge voltage, as the reduced inductance suppresses the L(di/dt) voltage spike even when di/dt is very large during fast switching
3Ease of manufacture
If the capacitor is placed far from switching elements to reduce interference, then layout flexibility is improved, but the connection path inductance increases and surge voltage is generated
Solution Approach 1:
The patent resolves the conflict between layout flexibility and inductance reduction by utilizing the vertical dimension. The capacitor can be positioned in the vertical stack above or below the switching elements, providing manufacturing flexibility in the vertical direction while maintaining minimal horizontal separation. This stacked configuration ensures short connection paths with low inductance regardless of the specific lateral layout arrangement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses surge voltages while maintaining rapid responsiveness and reducing inductance components, enhancing the semiconductor device's performance and efficiency.
Implementation Method 1
An inductance component of the connection path between this capacitor and the semiconductor device has a problem in which a surge voltage is generated
Data Source
AI summary
Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.