Stacked Semiconductor Test Pad Structure for Compact Probe Contact
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high integration and miniaturization of semiconductor devices, particularly in the design and layout of test pads, which affect the efficiency and size of semiconductor packages.
Innovation Solution
The semiconductor package design includes miniaturized wafer test pads that are smaller than package test pads, allowing for a more compact layout and efficient use of space, with the wafer test pads and package test pads being disposed in various configurations to reduce the overall size of the semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If test pads are made smaller to achieve miniaturization, then space efficiency is improved, but contact reliability deteriorates due to increased risk of contact defects
Solution Approach 1:
The test pad structure is segmented into multiple layers: a lower test pad layer and an upper test pad layer, with the upper layer positioned to overlap the lower layer. This segmentation allows each layer to contribute to contact reliability while maintaining overall miniaturization, as the overlapping configuration provides redundant contact paths without significantly increasing the footprint area.
Solution Approach 2:
The invention transitions from a two-dimensional test pad layout to a three-dimensional overlapping structure. By stacking test pads in vertical layers with overlapping horizontal projections, the design utilizes the vertical dimension to enhance contact reliability while keeping the horizontal footprint minimal, thus resolving the contradiction between size reduction and reliability maintenance.
2Productivity
If test pads are made smaller to reduce package size, then productivity is improved through better space utilization, but manufacturing precision requirements worsen due to finer pitch spacing
Solution Approach 1:
The test pad fabrication process is segmented into distinct stages: forming the lower test pad layer first, then forming the upper test pad layer with overlapping configuration. This segmentation allows standard fabrication processes to be used for each layer independently, avoiding the need for ultra-fine single-layer patterning while achieving high space utilization through the combined overlapping structure.
Solution Approach 2:
By utilizing the vertical dimension through overlapping layers, the invention achieves high space utilization without requiring proportionally finer horizontal pitch. The overlapping configuration in the vertical dimension compensates for coarser horizontal spacing, thereby maintaining manufacturing feasibility with standard precision processes while improving space efficiency.
3Volume of moving object
If wafer test pads are made smaller than package test pads, then device miniaturization is achieved, but test probe access becomes more difficult
Solution Approach 1:
The overlapping test pad structure extends in the vertical dimension, creating exposed portions that are accessible from the package exterior. This vertical extension allows probe cards to contact the upper test pad layer without requiring access to the interior wiring layers, thus maintaining ease of operation despite the miniaturized horizontal footprint and reduced overall package volume.
Solution Approach 2:
The upper test pad layer acts as an intermediary between the internal circuitry and external probe cards. By providing exposed overlapping portions on the package exterior, this intermediate structure enables testing of internal connections without requiring direct access to deeply embedded wiring, thus resolving the accessibility issue caused by miniaturization.
Data Source
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AI summary
A semiconductor package (10), includes: a base chip (100) having a front surface (FS) and a back surface (BS) opposite to the front surface (FS), the base chip (100) including bump pads (BP), wafer test pads (WTP), and package test pads (PTP), disposed on the front surface (FS); connection structures (20) disposed on the front surface (FS) of the base chip (100) and connected to the bump pads (BP); and semiconductor chips (200, 300, 400, 500) stacked on the back surface (BS) of the base chip (100), wherein each of the wafer test pads (WTP) is smaller than the package test pads (PTP).