Stacked TFET Active Regions for Parasitic Capacitance Reduction
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Solution Overview
Problem
Tunnel field-effect transistors (TFETs) face increased power consumption due to higher capacitance compared to MOS type FETs, primarily because the source and gate electrodes face each other through an insulation layer, leading to increased capacitance and power consumption.
Innovation Solution
The TFET configuration includes a first active region, a second active region positioned under the first active region, and a control electrode on the first active region, with specific overlapping and extension portions to create distinct capacitance regions, allowing for reduced power consumption by controlling the overlap and insulation between these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source electrode and gate electrode face each other through an insulation layer, then the TFET structure is formed, but the capacitance increases leading to higher power consumption
Solution Approach 1:
The gate electrode is segmented into a first gate electrode and a second gate electrode positioned at different heights. This segmentation allows the first gate electrode to control the tunnel barrier region while the second gate electrode controls the channel region, enabling independent optimization of tunneling efficiency and capacitance reduction to lower power consumption
Solution Approach 2:
The patent introduces a vertical dimension by positioning gate electrodes at different heights (first gate electrode above the tunnel barrier, second gate electrode above the channel). This three-dimensional gate configuration reduces parasitic capacitance between the source and gate while maintaining effective control over the tunneling current, thus reducing power consumption
2Reliability
If the control electrode overlaps with the first active region, then reliable TFET operation is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating different overlap configurations in different regions: the first gate electrode overlaps with the tunnel barrier region to enable reliable tunneling control, while the second gate electrode overlaps with the channel region to control carrier injection. This localized optimization allows reliable operation while managing parasitic capacitance through region-specific gate control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable operation by generating a difference in potential between overlap regions, facilitating tunnel current flow while reducing power consumption by minimizing parasitic capacitance and optimizing the overlap regions' capacitance.
Implementation Method 1
tunnel field-effect transistor
Data Source
AI summary
A tunnel field-effect transistor has a stacked structure including a second active region, a first active region, and a control electrode. The first active region includes a first-A active region and a first-B active region between the first-A active region and a first active region extension portion. A second active region exists below the first-A active region, and the second active region does not exist below the first-B active region. Where an orthographic projection image of the second active region and an orthographic projection image of the first active region overlap with each other is defined as L2-Total, and a length in a Y direction of the first active region is defined as L1-Y, when an axial direction of the first active region is defined as an X direction, and a stacked direction of the stacked structure is defined as a Z direction, L1-Y<L2-Total is satisfied.