Stacked TFT Array Substrate for High-PPI Aperture Gain

The patent transitions from a planar arrangement of thin film transistors to a three-dimensional stacked configuration. Multiple thin film transistors are arranged in different layers along the vertical direction, with their active regions overlapping in the planar view. This dimensional change reduces the occupied area on the substrate while maintaining transistor functionality through vertical stacking and selective connection to pixel electrodes.

The patent divides the thin film transistor structure into multiple independent layers, with each layer containing specific components (gate electrodes, active regions, source/drain electrodes). This segmentation allows different layers to be formed through separate manufacturing steps, enabling precise control over the position and connection of each component while reducing the overall occupied area and improving light transmittance.

The patent resolves the conflict between pixel density and aperture ratio by stacking thin film transistors in the vertical dimension. Multiple transistors share the same planar footprint through overlapping active regions, allowing higher pixel density without proportionally increasing the area occupied by wiring and transistors. This enables improved aperture ratio while maintaining high PPI.