Stacked TFT Array Layout for High-Resolution Display Panels
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Solution Overview
Problem
Conventional low-temperature polysilicon thin film transistor array substrates occupy a larger substrate area due to longer channels, restricting high resolution design in display panels.
Innovation Solution
A TFT array substrate design with two thin film transistors superposed in a perpendicular direction, electrically connected in series, reducing substrate area while maintaining effective channel length, using a through hole to connect drain and source regions of active layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a longer channel is provided to drive the thin film transistor in conventional low-temperature polysilicon array substrates, then the transistor can be driven effectively, but the substrate area occupied increases, restricting high resolution design
Solution Approach 1:
The patent transitions from a planar transistor layout to a three-dimensional stacked configuration where two active layers are positioned at different heights (first active layer on base substrate, second active layer above it). This vertical stacking enables the transistor channel to extend in the vertical dimension rather than only horizontally, thereby maintaining effective channel length for reliable transistor operation while reducing the horizontal footprint on the substrate, which directly addresses the contradiction between transistor driving capability and substrate area occupation.
Solution Approach 2:
The patent implements a nested structure where the second active layer is positioned above and overlaps with the first active layer in the vertical direction. The drain region of the first active layer connects to the source region of the second active layer through a through-hole, creating a vertically integrated transistor channel. This nesting arrangement allows the transistor function to be maintained with compact horizontal dimensions, resolving the area occupation issue while preserving driving capability.
2Measurement precision
If the number of small-sized thin film transistors is increased for high resolution display panels, then the resolution improves, but the process implementation difficulty and electrical performance requirements increase
Solution Approach 1:
By stacking two active layers vertically with their channels aligned in the vertical direction, the patent creates a compact transistor structure that occupies less horizontal space. This enables higher density transistor arrangements on the substrate, increasing the number of pixels per unit area and thereby improving display resolution. The vertical channel configuration also simplifies the interconnection architecture compared to planar layouts, helping to manage process complexity.
3Area of stationary object
If the channel length is reduced to decrease transistor area, then the substrate area is reduced, but the transistor driving capability and electrical performance deteriorate
Solution Approach 1:
The patent extends the transistor channel into the vertical dimension by stacking two active layers, where the channel path goes from the source region through the first active layer, connects via a through-hole to the second active layer, and extends through its channel to the drain region. This three-dimensional channel configuration maintains a sufficient effective channel length for good electrical performance and reliable transistor operation, while the horizontal projection of the transistor occupies minimal substrate area, thus resolving the contradiction between transistor area and electrical performance.
Data Source
Figure 1~3
Figure 4a~4d
AI summary
A TFT array substrate, a method for manufacturing the same, and a display device including such TFT array substrate are disclosed. The TFT array substrate includes a base substrate (100); and two thin film transistors located on the base substrate. The two thin film transistors each includes an active layer (102, 107) having a source region and a drain region, the two active layers of the two thin film transistors are superposed with each other in a direction perpendicular to the base substrate. The drain region of one of the two active layers is electrically connected to the source region of the other one of the two active layers so that the two thin film transistors are connected in series. Thus, it is possible to reduce or save an area occupied by each thin film transistor on the substrate while maintaining a total effective channel length constant, thereby facilitating a high resolution design of a display panel.