Stacked Thin Film Transistors Using BEOL Integration
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Solution Overview
Problem
The integration of multiple thin-film transistors (TFTs) at the back-end-of-line (BEOL) on a single substrate is challenging due to the difficulty in stacking and aligning them without additional substrates or layer transfer processes.
Innovation Solution
The integration of p-type amorphous semiconductor materials like Cu2O, NiO, and SiC is used to form p-type TFTs, allowing for the stacking of multiple TFTs at the BEOL on a single substrate, enabling complementary logic with both n-type and p-type TFTs, and eliminating the need for additional substrates or layer transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple TFTs are integrated at the BEOL on a single substrate, then device density and integration level are improved, but manufacturing complexity and alignment difficulty increase
Solution Approach 1:
The patent transitions from planar integration to vertical stacking by forming TFTs in multiple layers at the BEOL. The first TFT is formed in a first layer, then a first interlayer dielectric is deposited, followed by formation of a second TFT in a second layer above the first. This vertical dimensionality change enables higher device density while maintaining alignment through sequential layer formation processes.
Solution Approach 2:
The patent divides the integrated circuit into distinct layers separated by interlayer dielectric materials. Each TFT is segmented into its own layer with dedicated source, drain, and gate electrodes. The first interlayer dielectric layer separates the first TFT from the second TFT, enabling independent formation and alignment of each transistor layer while reducing mutual interference.
2Manufacturing precision
If additional substrates or layer transfer processes are used for stacking TFTs, then manufacturing precision is improved, but process complexity and cost increase
Solution Approach 1:
The patent merges multiple TFT formation processes into a single integrated BEOL fabrication sequence. Both the first TFT and second TFT are formed on the same substrate through continuous processing steps: forming the first TFT, depositing the first interlayer dielectric, then forming the second TFT. This eliminates the need for separate substrates or layer transfer operations, reducing process complexity while maintaining alignment precision through in-situ layer formation.
Solution Approach 2:
The patent performs preliminary formation of the first TFT and its associated electrodes and dielectric layers before forming the second TFT. The first interlayer dielectric layer is deposited and prepared in advance, providing a pre-configured foundation for the second TFT formation. This preliminary action ensures proper alignment and integration while simplifying the overall manufacturing process by avoiding post-formation alignment operations.
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.