Stacked TFT-Capacitor Structure for Compact Thin Displays
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Solution Overview
Problem
Existing semiconductor display technologies face challenges in reducing the size and thickness of displays due to the separate layout and stacking of thin-film transistors and capacitors, which occupy more layout area and hinder thickness reduction.
Innovation Solution
A semiconductor structure where a capacitor and a thin-film transistor are stacked on a substrate, with the upper electrode of the capacitor serving as the gate of the thin-film transistor, allowing for a shared conductive layer to reduce layout area and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thin-film transistor and capacitor are disposed separately on the substrate and electrically connected through circuit layers, then the electrical connectivity is ensured, but the layout area occupied increases
Solution Approach 1:
The patent merges the capacitor and thin-film transistor into a stacked configuration where the upper electrode of the capacitor serves dual purposes as both the capacitor electrode and the gate electrode of the thin-film transistor. This consolidation eliminates the need for separate circuit layers to connect the two components, thereby reducing the layout area while maintaining electrical connectivity through direct physical integration.
Solution Approach 2:
The upper electrode of the capacitor is designed to perform multiple functions: it serves as one of the capacitor electrodes for charge storage and simultaneously functions as the gate electrode of the thin-film transistor for controlling current flow. This multi-functionality reduces the total number of components and interconnect structures needed, thereby reducing the overall layout area.
2Area of stationary object
If the thin-film transistor and capacitor are stacked on the substrate and electrically connected through a circuit structure, then the layout area is reduced, but the thickness of the display increases
Solution Approach 1:
The patent implements a nested structure where the thin-film transistor is positioned directly on top of the capacitor, with the upper electrode of the capacitor serving as the gate electrode of the transistor. This nesting arrangement allows both components to occupy the same footprint area while maintaining compact vertical integration, effectively reducing the overall thickness compared to separate stacking approaches that require additional circuit structure layers.
3Reliability
If separate circuit layers are used to electrically connect the thin-film transistor and capacitor, then the electrical connectivity is ensured, but the manufacturing complexity increases
Solution Approach 1:
The patent combines the capacitor upper electrode and transistor gate electrode into a single structural element, eliminating the need for separate circuit layers to establish electrical connection between the capacitor and transistor. This merger simplifies the manufacturing process by reducing the number of deposition and patterning steps required compared to fabricating separate interconnect layers.
Data Source
AI summary
Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.