Stacked TFT Display Electrode Contacts to Reduce Active-Layer Damage
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Solution Overview
Problem
The manufacturing process of display devices often results in damage to semiconductor elements during the formation of thin film transistors, reducing their drivability and reliability due to exposure through holes of varying depths, and requires multiple masks, increasing production costs.
Innovation Solution
A method for manufacturing display devices that minimizes damage to semiconductor elements by forming thin film transistors in different layers with reduced mask usage, where contact holes are formed to connect source and drain electrodes through multiple insulating layers, enhancing transistor characteristics and reliability while reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are formed to expose semiconductor layers in conventional manufacturing processes, then electrical connections are established, but damage occurs to the semiconductor elements especially those exposed through shallow holes reducing drivability and reliability
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar transistor structure to a three-dimensional stacked structure where multiple transistor layers are vertically arranged. This allows contact holes to be formed at different depths to access different semiconductor layers, avoiding damage to shallower layers while maintaining electrical connectivity. The vertical stacking enables independent access to each transistor layer through selectively positioned contact holes.
Solution Approach 2:
The patent segments the transistor structure into multiple independent layers stacked vertically, with each layer containing complete transistor components (source, drain, active layer, gate electrode). This segmentation allows each layer to be accessed independently through separately formed contact holes, preventing damage propagation between layers and enabling selective electrical connection to specific transistor layers.
2Manufacturing precision
If multiple masks are used in the manufacturing process to form thin film transistors, then precise patterning is achieved, but manufacturing complexity and production costs increase
Solution Approach 1:
The patent merges multiple patterning operations into a single unified process by forming all transistor layers simultaneously from a common semiconductor layer using one mask pattern. The gate electrodes and source/drain structures of multiple layers are created in the same fabrication step, eliminating the need for separate masking and patterning operations for each layer, thus reducing manufacturing complexity while maintaining precision.
Solution Approach 2:
The patent creates a universal mask pattern that serves multiple functions simultaneously: it defines the geometry for gate electrodes, source/drain structures, and active regions across all transistor layers in a single patterning operation. This multi-functional mask design eliminates the need for layer-specific masks and reduces the total number of patterning steps required.
Data Source
AI summary
Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.