Stacked Thin Film Transistor Substrate for Compact Gate Driver Design
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Solution Overview
Problem
The challenge is to reduce the area required for gate drivers in display devices while maintaining high performance, as a large number of thin film transistors are needed in a limited space to minimize bezel size and improve manufacturing efficiency.
Innovation Solution
A thin film transistor substrate is designed with a first and second thin film transistor stacked vertically, where the second transistor's source/drain electrodes are connected to the first transistor's electrodes, and both share a common gate electrode, allowing for efficient use of space and reduced arrangement area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of thin film transistors are disposed in the gate driver to improve performance, then the performance of the display device is improved, but the area of the gate driver increases
Solution Approach 1:
The patent applies vertical stacking of thin film transistors to utilize the third dimension (height) for increasing transistor density. Multiple TFTs are arranged in vertical layers rather than only horizontal planes, allowing more transistors to be packed into the same footprint area, thus improving gate driver performance without increasing its planar area.
Solution Approach 2:
The patent implements nested arrangement where control lines and signal lines are embedded within vertical stacks of thin film transistors. The control lines are positioned between adjacent TFTs in the vertical stack, effectively nesting the interconnect structure within the transistor array, which reduces the overall gate driver area while maintaining full functionality.
2Area of stationary object
If the area of gate driver is reduced to minimize bezel area, then the bezel area is reduced, but the number of thin film transistors that can be disposed is limited
Solution Approach 1:
By transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking, the patent achieves higher transistor density within the same gate driver footprint. This allows more transistors to be disposed in a reduced area, enabling smaller bezel dimensions while maintaining the required number of TFTs for display performance.
Solution Approach 2:
The patent merges multiple functional layers into a compact vertical structure where active layers, gate electrodes, and control lines are integrated in overlapping vertical positions. This merging of spatial domains allows maximum utilization of the gate driver area, packing more transistors into a smaller footprint that directly reduces bezel size.
3Area of stationary object
If thin film transistors are arranged in a compact layout to reduce gate driver area, then the area is reduced, but the line connection efficiency deteriorates
Solution Approach 1:
The patent nests control lines within the vertical stack structure, positioning them between adjacent thin film transistors in the vertical arrangement. This nested configuration allows control lines to reach multiple TFTs efficiently without requiring extensive lateral routing, maintaining connection efficiency while achieving compact area reduction.
Solution Approach 2:
The patent resolves line connection complexity by utilizing vertical routing paths through the stacked structure. Instead of complex horizontal routing in a compact layout, signals are transmitted vertically through the stacked TFTs, simplifying the interconnect architecture and maintaining connection efficiency despite reduced gate driver area.
Data Source
AI summary
A thin film transistor substrate and a display device comprising the same are provided, in which the thin film transistor substrate comprises a first thin film transistor on a base substrate, and a second thin film transistor on the first thin film transistor, wherein the first thin film transistor includes a first active layer on the base substrate, a first gate electrode spaced apart from the first active layer, and a first source electrode and a first drain electrode, which are spaced apart from each other and connected to the first active layer, the second thin film transistor includes a second active layer on the base substrate, a second gate electrode spaced apart from the second active layer, and a second source electrode and a second drain electrode, which are spaced apart from each other and connected to the second active layer, and one of the first source electrode and the first drain electrode is connected to one of the second source electrode and the second drain electrode.