Stacked TFT Substrate Layout for Narrow-Bezel GIP Displays
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Solution Overview
Problem
The existing Gate-In-Panel (GIP) structure in display apparatuses requires a larger bezel size due to the size of the gate driver, necessitating a method to densely pack thin film transistors in a small area to reduce this size.
Innovation Solution
A thin film transistor substrate is designed with multiple transistors stacked vertically, featuring a first and second thin film transistor with active layers and gate electrodes, connected by a connection electrode through an insulating layer, allowing for efficient packing and reduced bezel size in display apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple thin film transistors are arranged horizontally in the Gate-In-Panel structure, then the transistors can be connected in series, but the bezel size increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of thin film transistors, utilizing the third dimension (height/depth) to increase transistor density. Multiple active layers are stacked vertically with connection electrodes penetrating through insulating layers to electrically connect transistors in different layers, thereby reducing the horizontal footprint and bezel area while maintaining the required number of transistors
Solution Approach 2:
The patent implements a nested structure where the second active layer is positioned above the first active layer, and connection electrodes are embedded within insulating layers to connect these nested layers. This nested arrangement allows multiple transistors to occupy overlapping horizontal space at different vertical levels, effectively reducing the overall area required for the Gate-In-Panel structure
2Area of stationary object
If thin film transistors are stacked vertically to reduce bezel size, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the thin film transistor structure into multiple discrete layers (first active layer, second active layer, insulating layers, connection electrodes) that can be manufactured separately and then assembled through vertical stacking. This segmentation allows each layer to be optimized and manufactured independently using standard thin film deposition techniques, reducing overall manufacturing complexity despite the three-dimensional architecture
Data Source
AI summary
Disclosed is a thin film transistor substrate comprising a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode; a first insulating layer between the first gate electrode and the second active layer; and; and a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer and a display apparatus including the same.