Stacked Thin Film Transistors for Narrow Border Display Panels
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Solution Overview
Problem
Current driving circuits face difficulties in designing narrow border displays due to the increasing complexity and inflexibility of gate driver on array (GOA) circuits with higher pixels per inch and narrower widths.
Innovation Solution
The implementation of a driving circuit with a first and second thin film transistor, where the second transistor is positioned on a leakage path between pull-down and pull-up control nodes, with its channel layer stacked above the first transistor's channel layer, allowing partial overlap and reducing the overall width occupied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If GOA circuits are designed with higher PPI and narrower widths, then display panel border width is reduced, but arrangement difficulty of TFTs and capacitors increases and design flexibility decreases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked arrangement of TFTs. Specifically, a second TFT is stacked above a first TFT, utilizing the vertical dimension to reduce the horizontal footprint of the GOA circuit, thereby enabling narrower borders while maintaining design flexibility and reducing arrangement difficulty.
Solution Approach 2:
The patent implements nested arrangement where the second TFT is positioned above and overlaps with the first TFT in the vertical direction. This nesting configuration allows multiple transistors to occupy the same horizontal space by stacking them vertically, effectively reducing the overall width of the GOA circuit.
2Length of stationary object
If GOA circuits are designed with higher PPI and narrower widths, then display panel border width is reduced, but design flexibility of GOA circuits decreases
Solution Approach 1:
By introducing the vertical stacking dimension, the patent provides additional design freedom. The stacked TFT configuration allows for more flexible circuit layout options and can be adapted to various GOA circuit designs, thereby maintaining or even enhancing design flexibility while achieving narrower borders.
3Reliability
If second thin film transistor is disposed on leakage path between pull-down control node and pull-up control node, then leakage current is reduced, but device structure becomes more complex
Solution Approach 1:
The patent combines the leakage protection function with the space-saving stacked structure. The second TFT, which blocks leakage current on the control node path, is integrated into the vertical stack with the first TFT. This merging of functions achieves both leakage reduction and compact structure simultaneously, rather than adding separate components.
Data Source
AI summary
The present invention provides an array substrate, a manufacturing method thereof, and a display panel. Orthographic projections of channel layers of two types of thin film transistors in a design of a driving circuit on the array substrate at least partially overlap, that is, two thin film transistors are stacked on top of each other, thereby facilitating a narrow border design of the display panel. In addition, a channel layer of one of the thin film transistors is an amorphous oxide semiconductor layer, which can reduce node leakage in the driving circuit, which is conducive to improving circuit stability and reducing power consumption.