Stacked Crystalline-Oxide TFT Layout for High-Resolution Pixels
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and resolution due to limitations in the design and fabrication of thin-film transistors, particularly in the integration of crystalline and oxide semiconductor materials, which affect the operational efficiency and reliability of pixel driving circuits in display devices.
Innovation Solution
The semiconductor device incorporates a dual-layer structure with a first thin-film transistor containing a crystalline semiconductor material and a second thin-film transistor containing an oxide semiconductor material, both with overlapping control electrodes, along with a capacitor structure that includes an oxide semiconductor pattern, to enhance integration density and resolution. This configuration allows for independent control of the transistors and improved pixel driving capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer thin-film transistor structure is used, then the fabrication process is simpler, but the integration density and resolution are limited
Solution Approach 1:
The patent transitions from a planar single-layer structure to a vertical dual-layer structure by stacking the first thin-film transistor and second thin-film transistor at different heights. This dimensional change allows both transistors to be formed within a compact footprint area, thereby achieving high integration density and improved resolution without significantly complicating the fabrication process
2Reliability
If crystalline semiconductor material is used in the first thin-film transistor, then the transistor provides good electrical performance, but the device complexity increases when integrating with oxide semiconductor materials
Solution Approach 1:
The patent divides the semiconductor device into two distinct functional segments: the first thin-film transistor using crystalline semiconductor material for high-performance electrical operations, and the second thin-film transistor using oxide semiconductor material for complementary functions. This segmentation allows each transistor type to be optimized independently while maintaining overall device manageability and reducing integration complexity
3Manufacturing precision
If the first and second thin-film transistors are vertically stacked, then the integration density is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent merges the fabrication processes for the first and second thin-film transistors by forming their respective semiconductor patterns, insulating layers, and control electrodes in an integrated sequence. The second thin-film transistor is constructed on top of the first transistor's structure, allowing both devices to be fabricated simultaneously through combined processing steps rather than separate sequential operations, thereby achieving high integration density without proportionally increasing fabrication complexity
Data Source
AI summary
A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern incudes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.


