Stacked Thin-Film Transistor Layout Without Via Lines
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Solution Overview
Problem
Traditional thin film transistors occupy a large area due to via lines, which hinders the reduction of volume and improvement of pixels per inch (PPI) in image displays.
Innovation Solution
A thin film transistor design where the source, drain, and gate layers are stacked together, with a gate insulating layer and semiconductor layer disposed on the sidewall, allowing electrical connection without via lines, and channel grooves and division grooves are defined to facilitate multiple transistor production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via lines are used to electrically connect source/drain to channel layer, then electrical connection is achieved, but occupied area increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. The source and drain electrodes are positioned above and below the channel layer respectively, creating vertical electrical connections that eliminate the need for lateral via lines. This dimensional change reduces the occupied area while maintaining reliable electrical connection.
Solution Approach 2:
The source and drain electrodes are nested in the vertical space above and below the channel layer, utilizing the third dimension for electrical connection. This nesting approach allows the current path to be embedded within the vertical structure rather than occupying lateral space, effectively reducing the footprint.
2Reliability
If via lines are used for source/drain connection, then electrical conduction is enabled, but volume increases
Solution Approach 1:
The invention moves the electrical connection path from the lateral plane to the vertical dimension. By positioning source and drain electrodes above and below the channel layer, the current flows vertically through the structure, significantly reducing the horizontal volume occupied by connection paths and improving pixel density.
3Ease of manufacture
If traditional parallel channel layer design is used, then manufacturing is simplified, but pixels per inch cannot be improved
Solution Approach 1:
The patent maintains manufacturing simplicity by using standard thin-film deposition techniques while achieving higher PPI through vertical stacking. The source, channel, and drain layers are deposited in sequence with precise thickness control, and the vertical configuration allows higher pixel density without significantly complicating the manufacturing process.
Solution Approach 2:
The invention changes the geometric parameters of the transistor structure by transitioning from a planar layout to a vertical stacked configuration. This parameter change reduces the area per pixel while maintaining manufacturability through controlled film thickness and stacking geometry, thereby enabling higher pixels per inch.
Data Source
AI summary
The present disclosure provides a thin film transistor, an electronic device, a manufacturing method of electronic device, and display device. The thin film transistor includes a driving circuit layer including a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer stacked together; wherein one of the first, the second, and the third metal layer is configured to be a gate, and the another two are configured to be a source and a drain; a gate insulating layer disposed on a sidewall of the driving circuit layer, and a semiconductor layer disposed on a surface of the gate insulating layer.