Stacked Thin-Film Memory Architecture for Higher Bitcell Density
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Solution Overview
Problem
Conventional embedded memory technologies are not stackable, leading to low density and limited bitcell density due to silicon-based limitations, which restricts the efficiency and capacity of integrated memory arrays.
Innovation Solution
A stackable thin film-based memory architecture using flexible substrates, incorporating thin film transistors and resistors, allows for increased memory cell density by enabling the stacking of memory cells, utilizing materials such as amorphous oxide semiconductors and resistance switching layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional silicon-based memory technology is used, then manufacturing process is well-established, but memory density is limited due to non-stackable architecture
Solution Approach 1:
The patent transitions from planar 2D memory layout to 3D vertical stacking architecture. Multiple memory layers are stacked above each other along the vertical dimension, with each layer containing complete bitcell structures. This dimensional change enables significantly higher memory density by utilizing the third dimension (height) rather than only expanding horizontally.
Solution Approach 2:
The patent implements nested structures where multiple functional components are integrated within vertical stacks. Memory layers are nested above each other, with conductive interconnect structures penetrating through multiple layers. The bitcell structures in each layer are nested within the overall stacked memory architecture, creating a compact hierarchical arrangement.
2Quantity of substance
If conventional 1T-1R bitcell structure is used, then transistor connectivity is simple, but area consumption is high limiting density
Solution Approach 1:
The patent reduces the planar footprint of each bitcell by stacking multiple bitcell layers vertically. Each individual bitcell maintains its functional structure but occupies reduced horizontal area because the overall memory capacity is achieved through vertical stacking of multiple such bitcells, effectively trading horizontal area for vertical height.
3Quantity of substance
If flexible substrates with thin film materials are used, then stackability and density are improved, but manufacturing precision challenges arise
Solution Approach 1:
The patent employs thin film deposition techniques to create precisely controlled layers with specific thicknesses and material properties. By controlling deposition parameters (temperature, pressure, material flux), the manufacturing process achieves the required precision for thin film transistor gates, dielectric layers, and conductive interconnects, enabling reliable stacked memory operation despite the complexity of thin film processing.
Data Source
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AI summary
A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.