Stacked Transistor Threshold Tuning via Patterned Dipole Layers
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Solution Overview
Problem
Providing multigate devices, such as fin-like field effect transistors and gate-all-around transistors, with multiple threshold voltages is challenging due to their small size, which limits the ability to tune their threshold voltages using different work function metals, and existing dipole engineering techniques have not been entirely satisfactory.
Innovation Solution
The use of patterned dipole dopant source layers that cover specific gate dielectric layers, followed by a thermal drive-in process, allows for the tuning of threshold voltages without the need for different work function metals, enabling the achievement of multiple threshold voltages by configuring the thickness and material characteristics of the dipole dopant source layers and the thermal drive-in process parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different work function metals are used to tune threshold voltages of multigate devices, then multiple threshold voltages can be achieved, but device complexity and manufacturing difficulty increase due to the need to integrate multiple metal layers
Solution Approach 1:
The patent changes the physical state and concentration parameters of dipole dopants within the gate dielectric layer to achieve different threshold voltages. By controlling the amount and distribution of dipole dopants rather than using different metals, the system achieves multiple threshold voltages without increasing structural complexity
Solution Approach 2:
The patent extracts the threshold voltage tuning function from the work function metal layer and relocates it to the gate dielectric layer through dipole dopant engineering. This separation allows the metal layer to maintain its primary function while the dielectric layer provides threshold voltage control
2Productivity
If device dimensions are reduced to enable further scaling, then productivity and production efficiency improve, but the ability to tune threshold voltages deteriorates due to minimal room for different work function metals
Solution Approach 1:
The patent transitions from horizontal/thickness-based metal layer approaches to vertical concentration-based dipole dopant distribution within the gate dielectric. This dimensional shift in the tuning mechanism allows for effective threshold voltage control even when overall device dimensions are reduced
Solution Approach 2:
The patent uses parameter changes in dipole dopant concentration and distribution within the gate dielectric to achieve threshold voltage tuning in scaled devices, replacing the need for varying metal layer thicknesses or compositions which become impractical at smaller dimensions
3Device complexity
If existing dipole engineering techniques are used to provide multiple threshold voltages, then different work function metals can be minimized or eliminated, but the techniques present challenges when device stacking is implemented
Solution Approach 1:
The patent applies segmentation by using multiple patterned dipole dopant source layers with different patterns to define different threshold voltage regions. This segmented approach allows selective doping of specific device regions and enables stacking configurations where different transistor stacks require different threshold voltages
Solution Approach 2:
The patent performs preliminary patterning of dipole dopant source layers before final device formation. This preliminary action establishes the threshold voltage profile early in the process, facilitating subsequent stacking operations and reducing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the modification of threshold voltages in transistors, providing 2N, 4, or 8 different threshold voltages without adding extra layers, enhancing the performance and reliability of integrated circuits by boosting speed and reducing power consumption.
Implementation Method 1
performing a thermal drive-in process, thereby driving dipole dopant from the patterned dipole dopant source layer into the gate dielectric
Data Source
AI summary
Dipole engineering techniques for stacked device structures are disclosed herein. According to various aspects of the present disclosure, an exemplary dipole engineering technique includes (1) forming at least two patterned dipole dopant source layers having different patterns and covering gate dielectric layers of some transistors, but not other transistors, (2) performing a thermal drive-in process (e.g., a dipole drive-in anneal), and (3) after removing the dipole dopant source layer, forming gate electrodes for the transistors, where a same gate electrode material is used for the transistors. Thickness(es) and/or material characteristics (e.g., dipole dopant) of the patterned dipole dopant source layers and/or parameters of the thermal drive-in process may be configured to achieve desired threshold voltages. Such technique may provide 2N threshold voltages (Vt), where N is a number of patterned dipole dopant source layers formed on the gate dielectric layers of the transistors to tune their threshold voltages.