Stacked Through-Via Structure for Narrower 3DIC Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller feature sizes and higher integration densities, which requires more efficient and creative fabrication techniques for semiconductor dies to accommodate the increasing demand for smaller electronic devices.
Innovation Solution
The formation of multiple, vertically-aligned through vias in semiconductor dies allows for the stacking of multiple dies to create 3D packages or 3D integrated circuits (3DICs), reducing the aspect ratio of each via and enabling the use of smaller widths for through vias, thereby providing more space for active and passive devices and conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If through vias are formed with smaller widths to increase integration density, then more components can be integrated into a given area, but the aspect ratio of the vias increases making fabrication more difficult
Solution Approach 1:
The patent divides a single long via into multiple shorter via segments stacked vertically. Each segment has a reduced aspect ratio compared to a single continuous via, making them easier to fill with conductive material. The segments are separated by dielectric layers, creating a stepped configuration that improves manufacturability while maintaining the overall via function.
Solution Approach 2:
The patent transitions from a single-dimensional via structure to a multi-dimensional stepped via structure by introducing vertical segmentation. The via is divided into multiple levels or stages, each at a different height, creating a three-dimensional configuration that reduces the effective aspect ratio of each individual via segment.
2Ease of manufacture
If traditional single via structures are used, then the fabrication process is simpler, but the available space for active and passive devices is reduced
Solution Approach 1:
The via structure is segmented into multiple shorter sections rather than forming one long via. This segmentation allows for better space utilization in the horizontal plane while maintaining vertical connectivity, thereby providing more room for active and passive devices without significantly complicating the fabrication process.
Solution Approach 2:
By introducing a stepped, multi-level via structure, the patent optimizes the use of three-dimensional space. The via occupies less horizontal area compared to a traditional via of equivalent vertical height, freeing up space for additional device structures while maintaining electrical connectivity through the stacked segments.
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.