Stacked Transistor Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
Previous approaches to reducing capacitance between adjacent gate and source/drain regions in transistors, such as using low-k spacer materials or increasing isolation material thickness, face challenges like increased fabrication difficulty and incompatibility with high-temperature processing.
Innovation Solution
The introduction of air gaps or low-k materials between stacked transistors to replace dielectrics, which reduces parasitic capacitance and improves device performance by selectively removing sacrificial materials and etching dielectrics to create horizontal and vertical air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If low-k spacer materials are used to reduce capacitance between adjacent gate and source/drain regions, then parasitic capacitance is reduced, but compatibility with high-temperature downstream processing is compromised
Solution Approach 1:
The patent extracts and removes the problematic low-k spacer material from the structure entirely. By etching away the low-k material and replacing it with air gaps, the solution eliminates the material compatibility issue while preserving the capacitance reduction benefit. The air gap serves as the isolation medium without suffering from high-temperature processing incompatibility.
Solution Approach 2:
The patent changes the dielectric parameter from a solid low-k material to an air gap (effectively changing the dielectric constant and material state). This parameter change allows the structure to achieve low capacitance while being compatible with high-temperature processing, as air gaps do not degrade under such conditions.
2Object-generated harmful factors
If the thickness of isolation material between stacked transistors is increased to reduce capacitance, then parasitic capacitance is reduced, but fabrication difficulty increases due to higher aspect ratios
Solution Approach 1:
Instead of increasing thickness in the vertical dimension (which worsens aspect ratio), the patent introduces air gaps in the lateral dimension between stacked transistors. This dimensional shift achieves capacitance reduction without compromising fabrication ease, as the air gaps are formed through selective etching rather than requiring thick material deposition.
Solution Approach 2:
The patent removes isolation material to create air gaps, thereby reducing capacitance without requiring additional thick material layers. This extraction approach avoids the fabrication difficulties associated with high aspect ratios while achieving the desired electrical isolation.
3Object-generated harmful factors
If air gaps are introduced between stacked transistors to reduce parasitic capacitance, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent incorporates air gap formation into the existing fabrication sequence by performing selective etching of low-k material and isolation material at an appropriate stage. By integrating the air gap creation process into the standard fabrication flow rather than adding a separate complex process, the solution minimizes overall process complexity while achieving capacitance reduction.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~2E
AI summary
A device is disclosed. The device includes a first gate conductor (111b) , a first source-drain region (109b, 109c) adjacent a first side of the first gate conductor and a second source-drain region (109b, 109c) adjacent a second side of the first gate conductor, a second gate conductor (111a) below the first gate conductor, a third source-drain region (109a, 109c) below the first source-drain region and adjacent a first side of the second gate conductor and a fourth source-drain region (109a, 109c) below the second source-drain region and adjacent a second side of the second gate conductor, a first air gap space (123) between the first source-drain region and a first side of the first gate conductor and a second air gap space (123) between the second source-drain region and the second side of the second gate conductor. A planar dielectric layer is formed above the first gate conductor.