Stacked Transistor Structure With Barrier Layer for Electrical Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration and miniaturization while maintaining improved electrical properties and reliability, particularly in stacked transistor structures.
Innovation Solution
The semiconductor device design includes a lower structure with source/drain regions and active layers connected by a gate structure, an upper structure with overlapping source/drain regions and active layers, and a barrier layer that contacts the uppermost and lowermost active layers, allowing for vertical stacking and isolation of source/drain regions with different conductivity types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain regions of lower and upper structures are directly formed without isolation, then manufacturing process is simplified, but electrical leakage and reliability deteriorate due to direct contact between source/drain regions of different conductivity types
Solution Approach 1:
A barrier layer is introduced as an intermediary structure between the lower and upper source/drain regions. This barrier layer physically separates regions of different conductivity types (n-type and p-type), preventing direct electrical contact and potential leakage paths, while still allowing the stacked transistor structure to function. The barrier layer acts as a mediator that enables both structures to coexist without electrical interference.
Solution Approach 2:
The device structure is segmented into distinct lower and upper structures with a barrier layer positioned between them. This segmentation divides the continuous structure into separate functional zones, allowing independent optimization of each transistor stack while maintaining electrical isolation. The barrier layer creates clear boundaries between n-type and p-type regions.
2Quantity of substance
If stacked transistor structure is implemented, then integration density is improved, but manufacturing precision requirements increase due to alignment of multiple layers
Solution Approach 1:
The transistor structure transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. By utilizing the vertical dimension, multiple transistor pairs can be stacked above each other, significantly increasing integration density without proportionally increasing the footprint area. The barrier layer and gate structures are extended into the third dimension to accommodate this vertical stacking.
3Reliability
If barrier layer is added between lower and upper structures, then electrical isolation is improved, but manufacturing process complexity increases
Solution Approach 1:
The barrier layer serves multiple functions simultaneously: it provides electrical isolation between n-type and p-type source/drain regions, acts as a physical separator between lower and upper structures, and enables the formation of the stacked transistor configuration. This multi-functionality reduces the need for additional specialized components or processes.
Data Source
AI summary
A semiconductor device includes a lower structure; a barrier layer on the lower structure; and an upper structure on the barrier layer, wherein the lower structure includes lower source/drain regions; lower active layers spaced apart from each other, between the lower source/drain regions; and a lower gate structure and including portions below each of the lower active layers, wherein the upper structure includes upper source/drain regions and vertically overlapping the lower source/drain regions; upper active layers spaced apart from each other, between the upper source/drain regions, and vertically overlapping the lower active layers; and an upper gate structure, including portions on each of the upper active layers, and vertically overlapping the lower gate structure, and wherein the uppermost lower active layer of the lower active layers and the lowermost upper active layer of the upper active layers are in contact with the barrier layer.