Stacked Transistor Barrier Structure for MOSFET Scaling Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operation characteristics, necessitating improved methods for fabricating high-performance stacked transistors.
Innovation Solution
A semiconductor device with stacked transistors is fabricated using a lower channel pattern and an upper channel pattern on a substrate, where the transistors are separated by first and second barrier patterns made of different materials, serving as potential barriers to prevent electrical diffusion and facilitate epitaxial growth of source/drain patterns, thereby enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size, then device density increases, but operation characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor layout to vertically stacked transistor structures (3D stacking), allowing multiple transistors to occupy a smaller footprint area while maintaining individual transistor performance characteristics through proper vertical spacing and isolation
2Ease of manufacture
If stacked transistors are fabricated without proper barrier structures, then manufacturing process is simpler, but electrical diffusion occurs between transistors
Solution Approach 1:
The patent introduces barrier patterns as intermediary structures between stacked transistors and source/drain regions. These barriers act as mediators that prevent unwanted electrical diffusion while maintaining the stacked configuration, with different materials used at different levels to provide comprehensive protection
3Ease of manufacture
If single material is used for barrier patterns, then manufacturing process is simpler, but epitaxial growth control is insufficient
Solution Approach 1:
The patent employs different materials for barrier patterns at different vertical levels (first barrier material at lower level, second barrier material at upper level). This local differentiation allows optimized epitaxial growth control at each level, with each material selected for its specific properties suitable for that position in the stacked structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the easy fabrication of stacked transistors with improved performance by electrically disconnecting lower and upper transistors and enabling efficient epitaxial growth of source/drain patterns, preventing transistor deterioration and enhancing overall device performance.
Implementation Method 1
the transistors are separated by first and second barrier patterns made of different materials, serving as potential barriers to prevent electrical diffusion
Implementation Method 2
facilitate epitaxial growth of source/drain patterns
Data Source
AI summary
A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.