Stacked Transistor Bonding Isolation Without Sacrificial Layers

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Solution Overview

Problem

Advanced integrated circuit (IC) technology faces challenges in manufacturing stacked transistor structures due to difficulties in removing sacrificial layers and filling gaps with dielectric material, leading to seam formation and reliability issues, as well as constraints on materials for semiconductor layers, which restricts the use of heterogeneous channel materials.

Innovation Solution

The proposed solution involves bonding and isolation techniques that eliminate the need for a sacrificial layer, allowing for the direct formation of an insulation layer between transistors without a gap fill step, enabling the use of heterogeneous channel materials and ultrathin bonding layers, and providing electrical isolation through monolithic or sequential fabrication methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sacrificial layers are used in stacked transistor fabrication, then transistor structures can be formed, but seam formation occurs and reliability deteriorates

Engineering Contradiction:
Improvedevice reliabilityVSAvoidseam formation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the sacrificial layer entirely from the fabrication process. Instead of using a sacrificial layer that must be removed later (causing seams), the invention directly forms the insulation layer between transistors, extracting the problematic intermediate step and eliminating the source of seam formation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The insulation layer is formed before the transistors are fully assembled into the stacked structure. This preliminary formation of the insulation layer prevents seam formation that would occur if the layer were formed after transistor assembly, as the insulation layer is already in place to guide subsequent material deposition without creating seams.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If gap fill steps are used to form insulation layers, then electrical isolation is achieved, but manufacturing complexity and process steps increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the formation of the insulation layer with the transistor fabrication process itself, rather than treating them as separate steps. The insulation layer is formed as part of the initial structure preparation, merging two previously separate operations (insulation layer formation and transistor assembly) into a single integrated process flow.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The insulation layer is formed preliminarily before transistor assembly, eliminating the need for subsequent gap fill steps. This preliminary action ensures electrical isolation is already in place when transistors are stacked, removing the complexity of post-assembly gap filling operations.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If homogeneous materials are used for semiconductor layers, then fabrication is simpler, but material versatility and device performance are restricted

Engineering Contradiction:
Improvefabrication simplicityVSAvoidmaterial selection flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent enables different semiconductor layers in the stacked structure to be made from different materials optimized for their specific functions. Each layer can have locally optimized material properties (e.g., different bandgaps, mobilities) without requiring the entire structure to use homogeneous materials, achieving local quality differentiation while maintaining overall structural integrity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240379748A1Bonding and Isolation Techniques for Stacked Transistor Structures
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379748A1 patent drawing
  • US20240379748A1 patent drawing
  • US20240379748A1 patent drawing

AI summary

Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.