Stacked Transistor Integration Density via Vertical Planar Bonding
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Solution Overview
Problem
The decreasing design rule in integrated circuit semiconductor devices leads to a short-channel effect and deterioration of current driving capability, necessitating improved integration density for both cell array and peripheral circuit transistors, while existing methods are complex and inefficient in achieving this.
Innovation Solution
The integration of vertical and planar transistors on a substrate with a bonding insulation layer and interconnection layer to enhance integration density, allowing for a simpler fabrication process by stacking transistors on separate substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the design rule is decreased to integrate more transistors in a limited substrate area, then integration density is improved, but short-channel effect occurs and current driving capability deteriorates
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, utilizing the third dimension (vertical direction) to increase integration density. The vertical transistor structure includes a gate electrode extending in the vertical direction, allowing more transistors to be packed in the same substrate area without reducing the effective gate width, thereby maintaining current driving capability while improving integration density.
2Quantity of substance
If vertical transistors are implemented to improve integration density, then more transistors can be integrated, but fabrication process complexity increases
Solution Approach 1:
The patent divides the fabrication process into separate sequential steps: forming the gate electrode structure first, then forming the source and drain regions subsequently. This segmentation allows each component to be fabricated independently with optimized processes, reducing overall fabrication complexity compared to attempting to form all structures simultaneously.
Solution Approach 2:
The gate electrode structure is formed in advance before the source and drain regions are created. This preliminary action establishes the vertical reference structure that guides subsequent processing steps, simplifying the overall fabrication sequence and reducing process complexity.
3Quantity of substance
If stacked transistors are formed on separate substrates with bonding insulation layer, then integration density is improved and fabrication is simplified, but additional bonding and interconnection steps are required
Solution Approach 1:
The bonding insulation layer is formed on the first substrate before bonding to the second substrate. This self-service approach prepares the bonding interface in advance, ensuring proper alignment and reducing the complexity of the bonding process itself, as the insulating structure is already in place to facilitate direct bonding without additional alignment steps.
Data Source
AI summary
An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.