Stacked Transistor-Capacitor Layout for Dense Oxide Semiconductor Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high productivity, miniaturization, high integration, high storage capacity, reliability, low off-state current, and efficient frequency characteristics while maintaining low power consumption and long data retention.
Innovation Solution
A semiconductor device comprising multiple transistors and capacitors with specific conductor and oxide configurations, including indium and other metal oxides, to enhance on-state current, reduce off-state current, and improve frequency characteristics, along with a manufacturing method that involves layer deposition and etching to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor devices are used, then manufacturing is straightforward, but productivity is low and integration density is limited
Solution Approach 1:
The semiconductor device is divided into multiple independent stacked layers (first transistor layer, second transistor layer, capacitor layer) that can be manufactured separately and then integrated. Each layer contains specific components (transistors with oxide semiconductor channels, capacitors) that are formed through distinct manufacturing processes, enabling modular production and higher integration density without proportionally increasing overall manufacturing complexity
Solution Approach 2:
The device transitions from planar two-dimensional layout to three-dimensional stacked configuration. Transistors and capacitors are arranged in vertical layers rather than horizontal planes, with the first transistor, second transistor, and capacitor forming stacked structures. This dimensional change increases integration capacity while maintaining manageable manufacturing processes for each layer
2Area of moving object
If device size is reduced for miniaturization, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into discrete stacked layers with clearly defined boundaries and functions. Each layer (first transistor layer, second transistor layer, capacitor layer) can be manufactured with standard precision requirements, and the modular nature allows for easier alignment and integration compared to attempting to miniaturize a monolithic structure, thereby reducing the overall manufacturing precision burden
Solution Approach 2:
Components are nested within each other in a vertical stacking configuration where the first transistor, second transistor, and capacitor are arranged in overlapping vertical layers. This nesting approach minimizes the horizontal footprint (device area) while each component maintains its structural integrity and can be manufactured with conventional precision, avoiding the need for extremely precise miniaturization
3Reliability
If oxide semiconductor transistors are used, then off-state current is reduced, but on-state current may be limited
Solution Approach 1:
The device employs a composite structure combining oxide semiconductor materials (for low off-state current and high reliability) with metal conductors (for high on-state current). The oxide semiconductor layer provides excellent off-state characteristics and data retention, while the metal conductor layers provide low resistance paths that enable high on-state current flow, thus combining the advantages of both material types to overcome their individual limitations
Data Source
AI summary
A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor.