Vertically Stacked Transistor Structures With Self-Aligned Channel Layers

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Solution Overview

Problem

The alignment and vertical separation of top and bottom devices in vertically stacked transistor structures are challenging in conventional processes, leading to complex and inefficient manufacturing flows.

Innovation Solution

A method for forming vertically stacked transistor structures by creating a first and second transistor structure from vertically stacked channel layers, using a sacrificial layer that is replaced by a dielectric layer to define the vertical separation, allowing for self-aligned channel layers and improved process control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional bonding processes are used to form vertically stacked transistor structures, then the top device can be bonded to the bottom device, but the alignment precision and vertical separation control become challenging and complex

Engineering Contradiction:
Improvealignment precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the channel layers in a stacked configuration before performing any bonding or separation operations. The first and second channel layers are deposited vertically stacked with the separating layer already in position, establishing the precise vertical separation and alignment relationships in advance. This eliminates the need for complex alignment operations during bonding and allows the vertical separation to be determined by the stack configuration rather than by bonding layer thickness control.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If bonding processes are used to join top and bottom devices, then the devices can be connected, but the active region definition and vertical separation become difficult to control

Engineering Contradiction:
Improvevertical separation controlVSAvoidprocess simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent introduces a separating layer as an intermediary element between the first and second channel layers. This separating layer serves as a mediator that defines the vertical separation distance independently of the bonding process. The separating layer can be formed with precise thickness control during the stacking process, and its presence allows the channel layers to be self-aligned while maintaining controlled vertical separation, simplifying the overall manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple separate processes are used to form top and bottom transistor structures, then each structure can be optimized, but the manufacturing flow becomes increasingly complex

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidprocess flow complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the formation of the first and second transistor structures into a single integrated process flow. By depositing the channel layers and separating layer in a stacked configuration during the same manufacturing sequence, the patent eliminates the need for separate bonding operations and multiple alignment processes. This combining approach maintains the ability to optimize each transistor structure while significantly simplifying the overall manufacturing flow and improving productivity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient definition of active regions and vertical separation in transistor structures, reducing manufacturing complexity and improving alignment precision, while allowing for complementary device configurations like NMOS and PMOS devices.

Implementation Method 1

The separating layer, which may be a dielectric layer comprising a semiconductor oxide or a metal oxide, may for instance be formed by replacing an epitaxially grown sacrificial layer with the dielectric layer.

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12563761B2Vertically stacked transistor structures
Publication Date: 2026.02.24 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US12563761B2 patent drawing
  • US12563761B2 patent drawing
  • US12563761B2 patent drawing

AI summary

A method for forming a first transistor structure from a first channel layer and a second transistor structure from a second channel layer is disclosed. The first channel layer and the second channel layer are vertically stacked on a substrate. The method includes processing the first transistor structure from above, followed by processing the second transistor structure from the backside.