Stacked Transistor Channel Regions Across Mixed Crystal Orientations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, the challenge arises in maintaining the performance of both p-type and n-type transistors without degrading one in favor of the other, particularly when channel regions are formed on substrates with different crystalline orientations.
Innovation Solution
The formation of complementary field-effect transistors (CFETs) with n-type and p-type nanostructure-FETs vertically stacked on substrates with different crystalline orientations, such as (100) and (110) oriented silicon substrates, allows for improved p-type transistor performance without compromising n-type transistor performance by separately growing channel materials on these substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then integration density is improved, but manufacturing precision and device performance deteriorate
Solution Approach 1:
The patent transitions from planar transistor layouts to three-dimensional stacked transistor structures. By stacking multiple transistor layers vertically, the device achieves higher integration density without proportionally reducing the minimum feature size in the lateral dimension. This dimensional transition allows maintaining manufacturing precision while increasing the number of transistors per unit area.
Solution Approach 2:
The patent employs composite material structures including alternating layers of semiconductor materials with different bandgaps (e.g., SiGe and Si) in the channel regions. This composite structure enables better control of carrier transport properties and allows for optimized device performance at scaled dimensions, addressing the performance deterioration that typically accompanies reduced minimum feature size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density and maintains or improves the performance of both p-type and n-type transistors by optimizing channel region growth on substrates with distinct crystalline orientations.
Implementation Method 1
the channel regions for the p-type transistors are formed on a (110) plane-oriented substrate, which can improve hole mobility in the p-type transistors
Implementation Method 2
the channel regions for the n-type transistors are formed on a (100) plane-oriented substrate, which can maintain electron mobility in the n-type transistors
Implementation Method 3
bonding layers can be deposited over the multi-layer stacks, and the (110) and (100) oriented substrates can be bonded together
Data Source
AI summary
A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.