Stacked Transistor Channel Recess for Mobility and Protection
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Solution Overview
Problem
Current integrated circuit devices face challenges in increasing integration density and carrier mobility, particularly in stacked transistor structures where the channel regions of transistors are not effectively protected and optimized for signal transmission.
Innovation Solution
The proposed integrated circuit device features a stacked transistor structure with a pair of thin semiconductor layers and channel regions of different materials, where the channel region is recessed to accommodate a gate insulator and gate electrode, enhancing carrier mobility and protection by using a capping layer and different conductivity types for the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked transistor structure is used to increase integration density, then integration density is improved, but channel region protection and carrier mobility are worsened
Solution Approach 1:
The channel region is segmented into multiple portions with different materials (e.g., SiGe for high mobility, Si for low mobility) along the channel length. This segmentation allows each segment to be optimized for specific functions: high mobility segments for carrier transport and low mobility segments for protection against hot carrier effects and electrical stress.
Solution Approach 2:
Different materials are used in different local regions of the channel. The channel includes a first channel portion with high mobility material (SiGe) and a second channel portion with low mobility material (Si). This local quality variation optimizes both carrier mobility in the transport region and device reliability in the protection region.
2Productivity
If stacked transistor structure is used to increase integration density, then integration density is improved, but carrier mobility is worsened
Solution Approach 1:
The channel is divided into multiple segments with different materials. High mobility material (SiGe) is placed in the first channel portion where carrier transport is critical, while low mobility material (Si) is placed in the second channel portion. This segmentation enables the device to achieve high integration density while maintaining high carrier mobility in the transport region.
Solution Approach 2:
The channel structure uses composite materials comprising different semiconductor materials (SiGe and Si) with different carrier mobility characteristics. This composite channel structure allows the device to leverage the high mobility of SiGe for fast carrier transport while using Si for device protection and stability.
3Speed
If different materials are used in channel regions, then carrier mobility is improved, but device complexity is worsened
Solution Approach 1:
The channel is segmented into a first channel portion and a second channel portion with different materials. This segmentation is implemented through a systematic fabrication process involving selective epitaxial growth or deposition, allowing complex material composition to be achieved through relatively simple process steps.
Solution Approach 2:
The material composition parameter is changed along the channel length to optimize carrier mobility. By varying the material composition (e.g., Ge content in SiGe) in different channel portions, the device achieves high carrier mobility without requiring complex three-dimensional structures or multiple stacked layers.
Data Source
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Figure 1C
AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices include a transistor on a substrate. The transistor includes: a pair of thin semiconductor layers (130) spaced apart from each other; a channel region (202) between the pair of thin semiconductor layers; a gate electrode on the pair of thin semiconductor layers and the channel region; and a gate insulator separating the gate electrode from both the pair of thin semiconductor layers and the channel region. A side surface of the channel region is recessed with respect to side surfaces of the pair of thin semiconductor layers and define a recess (204) between the pair of thin semiconductor layers. A portion of the gate insulator (122) and optionally a portion of the gate electrode is in the recess.