Stacked Transistor Gate and Channel Tuning for IC Density
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Solution Overview
Problem
Existing integrated circuit devices with stacked transistors lack the ability to independently adjust the lengths of gates, channels, and inner spacers between upper and lower devices, leading to uniform dimensions that hinder optimization and performance enhancement.
Innovation Solution
The solution involves forming stacked transistors with independently adjustable gate lengths, channel lengths, and inner spacer lengths by employing tapered and bowl etching processes, along with epitaxial growth of source/drain regions, allowing for asymmetric dimensions between upper and lower devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform dimensions are used for gates, channels, and inner spacers in stacked transistors, then manufacturing simplicity is maintained, but device performance and density optimization are hindered
Solution Approach 1:
The patent segments the gate, channel, and inner spacer dimensions into independently controllable parameters for upper and lower transistors. By introducing separate etching processes (first etching for lower transistor, second etching for upper transistor) and independent spacer formation steps, each transistor's dimensions can be optimized separately rather than being constrained by uniform dimensions across the stack.
Solution Approach 2:
The patent applies local quality by allowing different dimensional characteristics in different regions of the stacked transistor structure. The upper and lower transistors can have different gate lengths, channel lengths, and inner spacer lengths tailored to their specific performance requirements, rather than imposing a single uniform dimension across the entire structure.
2Productivity
If independent adjustment of gate, channel, and inner spacer lengths is implemented, then device performance and density are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the inner spacers before the final gate pattern definition. The inner spacers are formed as sacrificial structures that guide subsequent etching processes, allowing independent dimension control without requiring complex real-time adjustments during manufacturing.
Solution Approach 2:
The patent uses intermediary elements such as sacrificial layers and etch stop layers that facilitate independent dimension control. These intermediary structures enable the decoupling of upper and lower transistor dimension definition, allowing each to be optimized independently through selective etching processes without directly complicating the final device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables independent control of gate, channel, and inner spacer lengths, enhancing the performance and density of integrated circuit devices by optimizing the dimensions of upper and lower transistors.
Implementation Method 1
epitaxial growth of source/drain regions
Implementation Method 2
tapered and bowl etching processes
Implementation Method 3
tapered and bowl etching processes
Data Source
AI summary
An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.