Stacked Transistor Top Contacts With Self-Aligned Dielectric Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fabricating top contacts and corresponding interconnect structures for stacked transistors at small cell height and small back-end-of-line pitch is challenging due to the risk of shorting and failure, particularly at technology nodes below 20 nm.
Innovation Solution
The formation of merged top contacts and vias, followed by a self-aligned process to create a dielectric isolation region that separates these contacts, ensuring individual electrical connections without shorting, using high aspect ratio etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If top contacts are formed with close spacing to increase device density, then device integration density is improved, but the risk of shorting between adjacent contacts increases
Solution Approach 1:
The patent divides the continuous dielectric layer into segmented isolation regions that individually separate adjacent top contacts. Each isolation region acts as an independent barrier, ensuring that even at close spacing, electrical paths between neighboring contacts are completely blocked, thereby preventing shorting while maintaining high device density
Solution Approach 2:
The patent introduces dielectric isolation regions as intermediary structures between adjacent top contacts. These isolation regions serve as mediating elements that physically and electrically separate the contacts, allowing them to be placed closer together without direct electrical interaction, thus enabling higher density while maintaining reliability
2Manufacturing precision
If self-aligned process is used to form isolation regions, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent performs preliminary patterning of the dielectric layer to create isolation regions before forming the top contacts. This preliminary action establishes the isolation structure in advance, ensuring that subsequent contact formation is automatically aligned to these pre-defined isolation regions, thereby achieving high precision without requiring complex real-time alignment processes
Solution Approach 2:
The patent employs a self-aligned process where the isolation regions serve as their own alignment references. The top contacts are formed using the isolation regions as masks or guides, causing the contacts to automatically align themselves relative to the isolation structures without additional alignment steps, thus achieving high precision while simplifying the overall process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables individual electrical connections for adjacent stacked transistors with close spacing, reducing the risk of shorting and improving manufacturing yield.
Implementation Method 1
a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor
Data Source
AI summary
A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.