3D Stacked Transistor Contacts Beyond Lithography Scaling Limits
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in achieving high transistor density and performance due to limitations in scaling, particularly in single-digit nanometer nodes, where 2D circuits struggle to increase density beyond planar device constraints.
Innovation Solution
The method involves forming conductive elements for 3D semiconductor circuits using self-aligned contacts and punch-through operations to vertically align connections between stacked transistors, allowing for precise control of electron transport and device functionality, thereby exceeding density limits set by lithographic or resolution constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D circuits are used to increase transistor density, then area scaling can be achieved, but density is limited by planar device constraints at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertically stacked circuits, enabling transistors to be arranged in multiple layers above each other. This dimensional change allows transistor density to increase volumetrically rather than just areally, overcoming the planar scaling limitations at single-digit nanometer nodes while maintaining manufacturing feasibility through self-aligned fabrication processes
2Manufacturing precision
If lithographic processes are used to define minimum feature dimensions, then manufacturing precision can be achieved, but device density is limited by reticle resolution limits
Solution Approach 1:
The patent employs self-aligned fabrication processes where contact openings, trenches, and other features are defined by previously deposited spacer layers and masks. This preliminary structuring enables subsequent features to be precisely positioned without requiring additional high-resolution lithography steps, thereby achieving high device density while maintaining manufacturing precision through process-induced alignment rather than lithographic resolution alone
3Ease of manufacture
If conventional etching and deposition processes are used, then manufacturing simplicity can be maintained, but control of electron transport and device functionality is insufficient for dense stacked transistors
Solution Approach 1:
The patent utilizes selective etching processes with carefully controlled parameters including etch chemistry, temperature, pressure, and power settings to achieve precise depth control and selectivity between different material layers. These parameter changes enable reliable electron transport control in densely stacked transistors while maintaining ease of manufacture through standard semiconductor fabrication equipment and processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of densely packed semiconductor devices with improved performance by controlling ohmic losses and capacitance, and maintaining balanced operation between stacked transistors, surpassing the density achieved with traditional techniques.
Implementation Method 1
etching a surface of the semiconductor device to define a first recess
Implementation Method 2
filling the first recess with a first dielectric material
Data Source
AI summary
A method for fabricating semiconductor devices includes forming an opening. The method includes forming a blanket layer along vertical sidewalls of the opening. The method includes etching through the first recess through a first source/drain structure of the first semiconductor channel. The method includes filling the first recess with a dielectric material. The method includes removing the blanket layer between the dielectric material and the sidewall, to define a second and third recess opposite the dielectric material. The method includes etching the surface of the semiconductor device to define a fourth recess above a second source/drain structure of the first semiconductor channel. The method includes extending the third and fourth recesses through the first and second source/drain structures of the first semiconductor channel, to a first and second source/drain structure of the second semiconductor channel.