Vertically Stacked Transistor Assembly for Low-Inductance Cooling
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing size and minimizing parasitic inductance and thermal effects due to the relative placement and spacing of power electronic devices, gate drive devices, and capacitors, which impact performance.
Innovation Solution
A power electronics assembly with vertically stacked transistors connected by an electrical conductor and a busbar, combined with a hybrid cooling system using two-phase and single-phase cooling structures to enhance heat dissipation and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power electronic devices, gate drive devices and capacitors are placed separately in conventional semiconductor packages, then each component can be individually optimized, but the overall package size increases and parasitic inductance is generated due to spacing requirements
Solution Approach 1:
The patent combines power electronic devices, gate drive devices, and capacitors into a single integrated semiconductor package with vertically stacked transistors sharing common busbars. This merging eliminates the need for separate component placement and interconnections, thereby reducing overall package size while maintaining individual component optimization through the integrated design.
Solution Approach 2:
The patent transitions from conventional planar component layout to a vertical three-dimensional stacked architecture. By stacking transistors vertically and connecting them through shared busbars in the Z-dimension, the design reduces the horizontal footprint and overall package volume while maintaining electrical performance.
2Temperature
If power electronic devices are spaced apart to reduce thermal effects, then heat dissipation is improved, but the package size increases and parasitic inductance is generated
Solution Approach 1:
The patent integrates multiple power electronic devices into a compact stacked configuration where transistors share common busbars and are positioned in close proximity. This merging allows for optimized thermal management through controlled thermal paths while eliminating the need for large spacing, thereby reducing package size without sacrificing heat dissipation capability.
3Reliability
If transistors are connected through extensive busbar structures, then electrical connectivity is ensured, but parasitic inductance increases and device complexity increases
Solution Approach 1:
The patent merges multiple transistor connections into shared common busbars, where multiple transistors connect to the same busbar structures. This consolidation reduces the number of individual interconnections required, simplifying the overall device structure while ensuring reliable electrical connectivity through the shared busbar network.
Solution Approach 2:
The common busbars serve multiple functions simultaneously: they provide electrical connectivity for multiple transistors, act as thermal management pathways, and reduce parasitic inductance by minimizing current path lengths. This multi-functionality reduces overall device complexity while maintaining reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the overall size of the assembly while minimizing parasitic inductance and thermal effects, enhancing cooling efficiency and maintaining performance by distributing heat and electrical signals effectively.
Implementation Method 1
a first hybrid cooling assembly (102) disposed over the first power electronics module (104), a second hybrid cooling assembly (160) disposed over the second power electronics module (106)
Implementation Method 2
at least one electrical conductor that is positioned between the first and second transistors and electrically connected to the first and second transistors
Data Source
AI summary
Methods, apparatuses and systems provide technology that includes a first transistor, a second transistor stacked on the first transistor, at least one electrical conductor that is positioned between the first and second transistors and electrically connected to the first and second transistors, and a busbar that is electrically connected to the first and second transistors through the at least one electrical conductor.