Stacked Transistor Cross-Coupling via Local Interconnect Routing
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Solution Overview
Problem
The existing methods for forming cross-coupling between stacked transistors in semiconductor integrated circuits result in an area penalty due to the need to increase cell width and/or height, leading to inefficiencies in transistor design.
Innovation Solution
A transistor structure is proposed that includes a first transistor in a first layer, a second transistor in a second layer separated by an intermediate layer, a metal routing layer between the layers, and local interconnects connecting the transistors to the metal routing layer, allowing for cross-coupling without the area penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-coupling is formed for stacked transistors using existing methods, then the transistors can be connected between layers, but the cell width and/or height must be increased resulting in area penalty
Solution Approach 1:
The patent introduces an intermediate layer between the first and second transistor layers, creating a three-dimensional interconnect structure. The local interconnect extends vertically through the intermediate layer to connect transistors in different layers, utilizing the vertical dimension to reduce horizontal area requirements while maintaining reliable cross-coupling connections.
Solution Approach 2:
The intermediate layer acts as an intermediary structure that facilitates connections between stacked transistors. By introducing this intermediate layer with embedded local interconnects, the patent enables cross-coupling without requiring expansion of the cell footprint, as the intermediate layer provides a mediator pathway for signal transmission between layers.
2Reliability
If cell width and height are increased to accommodate cross-coupling formation, then cross-coupling can be achieved, but area penalty of up to 15% incurs
Solution Approach 1:
By moving the interconnect structure into the vertical dimension through the intermediate layer, the patent achieves cross-coupling functionality without increasing cell width or height. This dimensional transition maintains design efficiency by avoiding the 15% area penalty associated with traditional planar expansion methods.
3Area of stationary object
If local interconnect is used to connect transistors in stacked configuration, then area penalty is avoided, but additional intermediate layer and metal routing layer are required
Solution Approach 1:
The patent segments the interconnect function across multiple layers: the intermediate layer contains local interconnects for vertical connections, while the metal routing layer provides horizontal routing. This segmentation allows area-efficient stacking while distributing the complexity across specialized layers with distinct functions.
Solution Approach 2:
The intermediate layer serves multiple functions: it provides mechanical support between transistor layers, embeds local interconnects for vertical signal transmission, and integrates with the metal routing layer for comprehensive interconnect functionality. This multi-functionality justifies the additional layer by consolidating several requirements into a single structural element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient cross-coupling between transistors in stacked configurations without incurring the area penalties associated with existing methods, thereby improving the design efficiency and performance of semiconductor integrated circuits.
Implementation Method 1
an oxide bonding layer bonding the second transistor layer to the dielectric layer
Data Source
AI summary
Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.