Stacked Transistor Current Mirror for Deep-Submicron Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit manufacturing processes scale down to deep-submicron levels, the use of MOSFETs with long channel lengths becomes impractical, leading to current mismatches in current mirror circuits due to process variations, which are exacerbated by the need for smaller transistor sizes.
Innovation Solution
The solution involves stacking multiple transistors with short channel lengths in series to create equivalent transistors with long channel lengths, reducing current mismatch by configuring current mirror legs with these stacked transistors and strategically placing non-dominator transistors in regions with manufacturing variations within a transistor array to minimize mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MOSFETs with long channel lengths are used, then current mismatch is reduced, but device area increases and scaling is limited
Solution Approach 1:
The patent divides a single long-channel transistor into multiple short-channel transistors connected in series. Each transistor in the stack has a short channel length suitable for deep-submicron processes, but their series connection creates an equivalent long-channel transistor that reduces current mismatch while maintaining compact area.
Solution Approach 2:
The patent transitions from a planar single-transistor layout to a stacked three-dimensional configuration. By stacking transistors vertically in series, the design achieves equivalent long-channel performance without proportionally increasing the layout area, effectively utilizing the vertical dimension.
2Area of moving object
If process scaling is advanced to deep-submicron levels, then transistor size is reduced, but current mismatch increases due to process variations
Solution Approach 1:
The patent segments the channel into multiple short-channel transistors stacked in series. This segmentation allows each individual transistor to be fabricated with short channel length suitable for deep-submicron processes, while the series combination provides the equivalent electrical characteristics of a long-channel transistor, reducing sensitivity to process variations.
Solution Approach 2:
The patent changes the electrical parameters by connecting multiple transistors in series, transforming the equivalent channel length from short to long. This parameter transformation maintains compatibility with deep-submicron fabrication processes while achieving the current mismatch reduction typically associated with long-channel devices.
3Manufacturing precision
If stacked transistors are used to create equivalent long-channel transistors, then current mismatch is reduced, but device complexity increases
Solution Approach 1:
The patent creates a universal stacked transistor configuration that can be applied to various current mirror circuits and analog designs. The stacked transistor cell serves multiple functions: it provides equivalent long-channel behavior, maintains compatibility with standard deep-submicron processes, and can be replicated and arranged in arrays for different circuit requirements.
Solution Approach 2:
The patent employs replicated stacked transistor units arranged in arrays. By copying the basic stacked transistor configuration multiple times and arranging them in systematic patterns, the design achieves the desired current mirror performance while maintaining manufacturability through standard cell-based design methodologies.
4Area of moving object
If the entire transistor array area is utilized without dummy transistors, then area efficiency is improved, but manufacturing variations in corner regions affect performance
Solution Approach 1:
The patent applies different design treatments to different regions of the transistor array. Corner regions, which experience greater manufacturing variations, are assigned specific transistor types or configurations that are less sensitive to these variations. This local optimization maintains high area utilization while compensating for regional manufacturing challenges.
Solution Approach 2:
The patent incorporates compensation mechanisms directly into the transistor array design before fabrication. By pre-positioning compensation elements and configuring transistors to account for anticipated corner effects, the design proactively addresses manufacturing variations rather than requiring post-fabrication correction.
Data Source
AI summary
A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.