Stacked Transistor Discharging Path Through Isolation Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit devices with stacked transistors face challenges in secure isolation and charge dissipation, particularly due to the accumulation of plasma-induced charges that can lead to potential breakdown of gate dielectric layers, especially in the upper transistor structure where the middle isolation layer acts as a barrier for charge discharge.
Innovation Solution
Incorporating a diode structure as part of a discharging path between the gate electrode of the upper transistor structure and the substrate, which extends through the isolation layer, providing a pathway for charges to dissipate and preventing accumulation, thus enhancing the reliability and performance of the integrated circuit device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a middle isolation layer is used to provide secure isolation between stacked transistor structures, then isolation between elements is improved, but charge dissipation is hindered causing plasma-induced charge accumulation
Solution Approach 1:
A discharging path structure is introduced as an intermediary element that extends through the middle isolation layer. This path includes a discharging electrode connected to the upper transistor gate and a discharge electrode connected to the substrate, with an intervening dielectric layer. The intermediary structure provides a controlled pathway for charge dissipation while preserving the isolation function of the middle isolation layer, thus resolving the contradiction between secure isolation and charge dissipation.
2Stability of the object's composition
If the middle isolation layer is positioned between lower and upper channel layers, then structural isolation is achieved, but charge discharge is blocked leading to potential gate dielectric breakdown
Solution Approach 1:
The isolation and charge management functions are segmented into separate structures. The middle isolation layer maintains structural isolation between the lower and upper channel layers, while the discharging path structure (comprising discharging electrode, discharge electrode, and intervening dielectric) is positioned adjacent to the upper transistor to handle charge dissipation. This segmentation allows each structure to perform its specialized function without compromising the other, preventing gate dielectric breakdown while preserving structural isolation.
3Productivity
If stacked transistor structures are implemented to increase device density, then productivity is improved, but charge management complexity increases due to isolation layer barriers
Solution Approach 1:
The charge management approach transitions from a planar configuration to a three-dimensional structure. The discharging path extends vertically through the middle isolation layer, utilizing the vertical dimension to create a direct charge dissipation pathway. This dimensional change allows charge management to occur in parallel with the stacked transistor structure without increasing lateral footprint, thus maintaining high device density while simplifying charge management through the added vertical pathway.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diode structure effectively dissipates plasma-induced charges, preventing potential breakdown of gate dielectric layers and improving the reliability and performance of the integrated circuit device by ensuring secure isolation and reliable charge management.
Implementation Method 1
The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.
Data Source
AI summary
Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.