Vertically Stacked Transistors for High-Density DRAM
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Solution Overview
Problem
High integration density in semiconductor memory devices leads to reliability issues, necessitating improvements in design to enhance performance and efficiency.
Innovation Solution
A semiconductor memory device design featuring vertically stacked transistors with a 2T1C DRAM cell configuration, utilizing amorphous oxide semiconductor layers and a specific arrangement of gate and capacitor electrodes to reduce cell area and improve integration density, along with a detailed manufacturing process to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration density is achieved by reducing element widths, then integration density is improved, but reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor layout to vertical 3D stacked transistor configuration. Multiple transistor layers are stacked vertically with shared source/drain regions, enabling higher integration density without proportionally reducing element dimensions, thereby maintaining reliability while increasing capacity.
Solution Approach 2:
The patent implements nested structure where multiple transistor layers are contained within a vertical stack, with lower transistors nested beneath upper transistors. The source/drain regions of lower transistors serve as part of the structure for upper transistors, creating a compact nested arrangement that improves density without compromising individual transistor performance.
2Quantity of substance
If vertical stacking of transistors is implemented, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent employs shared source/drain regions that serve multiple functions: they act as source/drain for lower transistors and simultaneously as part of the gate structure or isolation for upper transistors. This multi-functionality reduces the number of separate components needed, simplifying manufacturing despite the vertical complexity.
Solution Approach 2:
The patent merges adjacent source/drain regions across multiple transistor layers into unified continuous structures. Instead of creating separate source/drain regions for each transistor layer, the design combines them into shared regions that extend vertically, reducing fabrication steps and material usage while maintaining electrical functionality.
Data Source
AI summary
A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.