Stacked Transistor Driver Circuit for Narrow Bezel Displays

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Solution Overview

Problem

Display devices, such as liquid crystal and EL displays, face challenges in achieving a narrow bezel design due to the size and complexity of driver circuits, which hinder miniaturization and design flexibility.

Innovation Solution

A display device with a driver circuit structure that includes a selection circuit and a buffer circuit with stacked transistors, allowing for a reduced bezel width by dividing the buffer circuit into two transistors and overlapping them, enabling a more compact design while maintaining high visibility and low power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the driver circuit is formed using conventional CMOS circuits or transistors, then the circuit functionality is achieved, but the bezel width remains large due to the circuit size

Engineering Contradiction:
Improvebezel widthVSAvoiddriver circuit size
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent applies stacked transistor structures where transistors are arranged in vertical layers rather than horizontal planes. Specifically, a first transistor and a second transistor are stacked with their active regions overlapping, allowing the driver circuit to utilize the vertical dimension for circuit integration. This dimensional transition from 2D planar layout to 3D stacked architecture significantly reduces the horizontal footprint of the driver circuit, enabling narrower bezel widths while maintaining full circuit functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The driver circuit is segmented into multiple functional blocks including a shift register circuit divided into first and second shift register circuits, and a buffer circuit with stacked transistors. This segmentation allows for optimized layout of each sub-circuit, enabling more efficient space utilization and contributing to overall circuit miniaturization that reduces bezel width.

Inventive Principle:
Principle #1Segmentation

2Length of stationary object

If the driver circuit size is reduced to narrow the bezel, then the bezel width decreases, but the circuit layout becomes more complex

Engineering Contradiction:
Improvebezel widthVSAvoidcircuit layout complexity
Core Design Contradiction:
Length of stationary objectVSEase of manufacture

Solution Approach 1:

By transitioning to stacked transistor structures, the patent simplifies the horizontal layout complexity. The vertical stacking of transistors with overlapping active regions provides a systematic approach to circuit miniaturization that follows clear manufacturing guidelines, making the reduced layout as manufacturable as conventional designs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The stacked transistor structure serves multiple functions: it reduces circuit footprint, maintains electrical performance, and provides a scalable architecture for different driver circuit configurations. This universal structure can be applied to various circuit blocks (shift registers, buffers, etc.), simplifying the overall design process despite the reduced bezel width requirement.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If transistors are stacked with overlapping regions to reduce area, then the driver circuit area is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedriver circuit areaVSAvoidtransistor alignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The stacked transistor architecture utilizes vertical layering with controlled overlapping of active regions. This approach reduces the horizontal circuit area while the overlapping design inherently provides alignment tolerance, as the vertical stack structure allows for controlled overlap that compensates for manufacturing variations, thereby managing precision requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The design incorporates overlapping active regions between stacked transistors as a built-in cushioning mechanism. This overlap provides a margin of error that compensates for potential misalignment during manufacturing, ensuring reliable electrical connections and transistor operation even when alignment precision varies within acceptable ranges.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Length of stationary object

If the driver circuit is integrated on the same substrate to reduce bezel, then the bezel width narrows, but the visibility of the display area may be affected

Engineering Contradiction:
Improvebezel widthVSAvoiddisplay visibility
Core Design Contradiction:
Length of stationary objectVSIllumination intensity

Solution Approach 1:

By stacking transistors vertically, the patent reduces the horizontal space required for the driver circuit, allowing the display area to extend closer to the edges of the substrate. This increases the effective display area and improves visibility, as more of the substrate surface is dedicated to the visible display region rather than circuitry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10460647B2Display device and electronic device
Publication Date: 2019.10.29 SEMICON ENERGY LAB CO LTD
  • US10460647B2 patent drawing
  • US10460647B2 patent drawing
  • US10460647B2 patent drawing

AI summary

A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit provided on one plane. The driver circuit includes a selection circuit and a buffer circuit. The buffer circuit includes a first transistor and a second transistor. Sources of the first and second transistors are electrically connected with each other. Drains of the first and second transistors are electrically connected with each other. Gates of the first and second transistors are electrically connected with each other. The first transistor and the second transistor are stacked so that the direction of the current flow in the first transistor is parallel to that in the second transistor.